clk: qcom: gcc-sm8450: Set delay for Venus CLK resets

Some Venus resets may require more time when toggling. Describe that.

The value is known for SM8450, see [1].

[1] https://git.codelinaro.org/clo/la/platform/vendor/opensource/video-driver/-/commit/d0730ea5867264ee50b793f6700eb6a376ddcbbb

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240105-topic-venus_reset-v2-11-c37eba13b5ce@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/drivers/clk/qcom/gcc-sm8450.c b/drivers/clk/qcom/gcc-sm8450.c
index 563542982551601cd2bb1acda4b0e8e38eec6f85..1825b3456dd06ccccbe6d9e98c755ef3842692d8 100644 (file)
--- a/drivers/clk/qcom/gcc-sm8450.c
+++ b/drivers/clk/qcom/gcc-sm8450.c
@@ -3202,8 +3202,8 @@ static const struct qcom_reset_map gcc_sm8450_resets[] = {
        [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x60004 },
        [GCC_USB3PHY_PHY_SEC_BCR] = { 0x60010 },
        [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x7a000 },
-       [GCC_VIDEO_AXI0_CLK_ARES] = { 0x42018, 2 },
-       [GCC_VIDEO_AXI1_CLK_ARES] = { 0x42020, 2 },
+       [GCC_VIDEO_AXI0_CLK_ARES] = { .reg = 0x42018, .bit = 2, .udelay = 1000 },
+       [GCC_VIDEO_AXI1_CLK_ARES] = { .reg = 0x42020, .bit = 2, .udelay = 1000 },
        [GCC_VIDEO_BCR] = { 0x42000 },
 };