drm/i915/dp: Initialize the link parameters during HW readout

Initialize the DP link parameters during HW readout. These need to be
up-to-date at least for the MST topology probing, which depends on the
link rate and lane count programmed in DPCD. A follow-up patch will
program the DPCD values to reflect the maximum link parameters before
the first MST topology probing, but should do so only if the link is
disabled (link_trained==false).

Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240722165503.2084999-6-imre.deak@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 86412ae7b48f72a575e55ed8abeb6f96752a3cbb..32964e15f3b11a49e0180334690f13b8e085430d 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3352,8 +3352,11 @@ void intel_dp_sync_state(struct intel_encoder *encoder,
 
        intel_dp_tunnel_resume(intel_dp, crtc_state, dpcd_updated);
 
-       if (crtc_state)
+       if (crtc_state) {
                intel_dp_reset_link_params(intel_dp);
+               intel_dp_set_link_params(intel_dp, crtc_state->port_clock, crtc_state->lane_count);
+               intel_dp->link_trained = true;
+       }
 }
 
 bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,