<&qos_cif1>,
<&qos_ipp>,
<&qos_rga>;
+ #power-domain-cells = <0>;
};
power-domain@RK3066_PD_VIDEO {
<&cru HCLK_VDPU>,
<&cru HCLK_VEPU>;
pm_qos = <&qos_vpu>;
+ #power-domain-cells = <0>;
};
power-domain@RK3066_PD_GPU {
reg = <RK3066_PD_GPU>;
clocks = <&cru ACLK_GPU>;
pm_qos = <&qos_gpu>;
+ #power-domain-cells = <0>;
};
};
};
<&qos_cif0>,
<&qos_ipp>,
<&qos_rga>;
+ #power-domain-cells = <0>;
};
power-domain@RK3188_PD_VIDEO {
<&cru HCLK_VDPU>,
<&cru HCLK_VEPU>;
pm_qos = <&qos_vpu>;
+ #power-domain-cells = <0>;
};
power-domain@RK3188_PD_GPU {
reg = <RK3188_PD_GPU>;
clocks = <&cru ACLK_GPU>;
pm_qos = <&qos_gpu>;
+ #power-domain-cells = <0>;
};
};
};
<&qos_vio2_rga_r>,
<&qos_vio2_rga_w>,
<&qos_vio1_isp_r>;
+ #power-domain-cells = <0>;
};
/*
<&cru SCLK_HEVC_CORE>;
pm_qos = <&qos_hevc_r>,
<&qos_hevc_w>;
+ #power-domain-cells = <0>;
};
/*
clocks = <&cru ACLK_VCODEC>,
<&cru HCLK_VCODEC>;
pm_qos = <&qos_video>;
+ #power-domain-cells = <0>;
};
/*
clocks = <&cru ACLK_GPU>;
pm_qos = <&qos_gpu_r>,
<&qos_gpu_w>;
+ #power-domain-cells = <0>;
};
};