drm/i915/icl: Add register definition for DFLEXDPMLE

DFLEXDPMLE register is required to tell the FIA hardware which
main links of DP are enabled on TCC Connectors. FIA uses this
information to program PHY to Controller signal mapping.
This register is applicable in both TC connector's Alternate mode
as well as DP connector mode.

v2:
* Remove _ICL prefix since the reg is first introduced
in ICL (Paulo)
* s/ICL/icl in commit message (Lucas)

Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Animesh Manna <animesh.manna@intel.com>
Cc: Madhav Chauhan <madhav.chauhan@intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1527275032-4555-1-git-send-email-manasi.d.navare@intel.com

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 43397e50fec371a9c057a015f846ce6b6b48ad95..5866b7d0ad818dbba6c4945bb65b6670f9adf8d8 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1990,6 +1990,11 @@ enum i915_power_well_id {
                                                   _ICL_PORT_COMP_DW10_A, \
                                                   _ICL_PORT_COMP_DW10_B)
 
+/* ICL PHY DFLEX registers */
+#define PORT_TX_DFLEXDPMLE1            _MMIO(0x1638C0)
+#define   DFLEXDPMLE1_DPMLETC_MASK(n)  (0xf << (4 * (n)))
+#define   DFLEXDPMLE1_DPMLETC(n, x)    ((x) << (4 * (n)))
+
 /* BXT PHY Ref registers */
 #define _PORT_REF_DW3_A                        0x16218C
 #define _PORT_REF_DW3_BC               0x6C18C