drm/amd/display: Fix some HostVM parameters in DML

[Why]
A number of DML parameters related to HostVM were either missing or
being set incorrectly, which may cause inaccuracies in calculating
margins and determining BW limitations.

[How]
Correct these values where needed and populate the missing values.

Cc: stable@vger.kernel.org
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Taimur Hassan <syed.hassan@amd.com>
Signed-off-by: Roman Li <Roman.Li@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
index 21c17d3296a3c8b8489966cb3eb8797e71896780..39cf1ae3a3e16238f59e16db69556a6156cef067 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
@@ -330,6 +330,39 @@ void dcn35_update_bw_bounding_box_fpu(struct dc *dc,
        dml_init_instance(&dc->dml, &dcn3_5_soc, &dcn3_5_ip,
                                DML_PROJECT_DCN31);
 
+       /*copy to dml2, before dml2_create*/
+       if (clk_table->num_entries > 2) {
+
+               for (i = 0; i < clk_table->num_entries; i++) {
+                       dc->dml2_options.bbox_overrides.clks_table.num_states =
+                               clk_table->num_entries;
+                       dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dcfclk_mhz =
+                               clock_limits[i].dcfclk_mhz;
+                       dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].fclk_mhz =
+                               clock_limits[i].fabricclk_mhz;
+                       dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dispclk_mhz =
+                               clock_limits[i].dispclk_mhz;
+                       dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dppclk_mhz =
+                               clock_limits[i].dppclk_mhz;
+                       dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].socclk_mhz =
+                               clock_limits[i].socclk_mhz;
+                       dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].memclk_mhz =
+                               clk_table->entries[i].memclk_mhz * clk_table->entries[i].wck_ratio;
+                       dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dcfclk_levels =
+                               clk_table->num_entries;
+                       dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_fclk_levels =
+                               clk_table->num_entries;
+                       dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dispclk_levels =
+                               clk_table->num_entries;
+                       dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dppclk_levels =
+                               clk_table->num_entries;
+                       dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_socclk_levels =
+                               clk_table->num_entries;
+                       dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_memclk_levels =
+                               clk_table->num_entries;
+               }
+       }
+
        /* Update latency values */
        dc->dml2_options.bbox_overrides.dram_clock_change_latency_us = dcn3_5_soc.dram_clock_change_latency_us;
 

diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c b/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c
index 48caa34a5ce75db3ceb5606b4f120db5e619d920..fa8fe5bf7e57566fdb897dfe891692a9d2db781c 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c
@@ -1057,9 +1057,12 @@ void map_dc_state_into_dml_display_cfg(struct dml2_context *dml2, struct dc_stat
        }
 
        //Generally these are set by referencing our latest BB/IP params in dcn32_resource.c file
-       dml_dispcfg->plane.GPUVMEnable = true;
-       dml_dispcfg->plane.GPUVMMaxPageTableLevels = 4;
-       dml_dispcfg->plane.HostVMEnable = false;
+       dml_dispcfg->plane.GPUVMEnable = dml2->v20.dml_core_ctx.ip.gpuvm_enable;
+       dml_dispcfg->plane.GPUVMMaxPageTableLevels = dml2->v20.dml_core_ctx.ip.gpuvm_max_page_table_levels;
+       dml_dispcfg->plane.HostVMEnable = dml2->v20.dml_core_ctx.ip.hostvm_enable;
+       dml_dispcfg->plane.HostVMMaxPageTableLevels = dml2->v20.dml_core_ctx.ip.hostvm_max_page_table_levels;
+       if (dml2->v20.dml_core_ctx.ip.hostvm_enable)
+               dml2->v20.dml_core_ctx.policy.AllowForPStateChangeOrStutterInVBlankFinal = dml_prefetch_support_uclk_fclk_and_stutter;
 
        dml2_populate_pipe_to_plane_index_mapping(dml2, context);