x86: Remove __FORCE_ORDER workaround

GCC PR82602 that caused invalid scheduling of volatile asms:

  https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82602

was fixed for gcc-8.1.0, the current minimum version of the
compiler required to compile the kernel.

Remove workaround that prevented invalid scheduling for
compilers, affected by PR82602.

There were no differences between old and new kernel object file
when compiled for x86_64 defconfig with gcc-8.1.0.

Signed-off-by: Uros Bizjak <ubizjak@gmail.com>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Cc: Andy Lutomirski <luto@kernel.org>
Cc: Brian Gerst <brgerst@gmail.com>
Cc: Juergen Gross <jgross@suse.com>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Kees Cook <keescook@chromium.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Josh Poimboeuf <jpoimboe@redhat.com>
Link: https://lore.kernel.org/r/20250407112316.378347-1-ubizjak@gmail.com

diff --git a/arch/x86/include/asm/debugreg.h b/arch/x86/include/asm/debugreg.h
index fdbbbfec745aa58855641ae59e17a3a50fc2696a..719d95f1ab5eec9e3846a7a143696b37a69fa7c3 100644 (file)
--- a/arch/x86/include/asm/debugreg.h
+++ b/arch/x86/include/asm/debugreg.h
@@ -23,7 +23,7 @@ DECLARE_PER_CPU(unsigned long, cpu_dr7);
 
 static __always_inline unsigned long native_get_debugreg(int regno)
 {
-       unsigned long val = 0;  /* Damn you, gcc! */
+       unsigned long val;
 
        switch (regno) {
        case 0:
@@ -43,7 +43,7 @@ static __always_inline unsigned long native_get_debugreg(int regno)
                break;
        case 7:
                /*
-                * Apply __FORCE_ORDER to DR7 reads to forbid re-ordering them
+                * Use "asm volatile" for DR7 reads to forbid re-ordering them
                 * with other code.
                 *
                 * This is needed because a DR7 access can cause a #VC exception
@@ -55,7 +55,7 @@ static __always_inline unsigned long native_get_debugreg(int regno)
                 * re-ordered to happen before the call to sev_es_ist_enter(),
                 * causing stack recursion.
                 */
-               asm volatile("mov %%db7, %0" : "=r" (val) : __FORCE_ORDER);
+               asm volatile("mov %%db7, %0" : "=r" (val));
                break;
        default:
                BUG();
@@ -83,15 +83,15 @@ static __always_inline void native_set_debugreg(int regno, unsigned long value)
                break;
        case 7:
                /*
-                * Apply __FORCE_ORDER to DR7 writes to forbid re-ordering them
+                * Use "asm volatile" for DR7 writes to forbid re-ordering them
                 * with other code.
                 *
                 * While is didn't happen with a DR7 write (see the DR7 read
                 * comment above which explains where it happened), add the
-                * __FORCE_ORDER here too to avoid similar problems in the
+                * "asm volatile" here too to avoid similar problems in the
                 * future.
                 */
-               asm volatile("mov %0, %%db7"    ::"r" (value), __FORCE_ORDER);
+               asm volatile("mov %0, %%db7"    ::"r" (value));
                break;
        default:
                BUG();

diff --git a/arch/x86/include/asm/special_insns.h b/arch/x86/include/asm/special_insns.h
index 6266d6b9e0b8c0ba9a218828e0cf72c1ffda3c26..ecda17efa042d2e9291b5b9d3f0b294900555b11 100644 (file)
--- a/arch/x86/include/asm/special_insns.h
+++ b/arch/x86/include/asm/special_insns.h
@@ -10,30 +10,19 @@
 #include <linux/irqflags.h>
 #include <linux/jump_label.h>
 
-/*
- * The compiler should not reorder volatile asm statements with respect to each
- * other: they should execute in program order. However GCC 4.9.x and 5.x have
- * a bug (which was fixed in 8.1, 7.3 and 6.5) where they might reorder
- * volatile asm. The write functions are not affected since they have memory
- * clobbers preventing reordering. To prevent reads from being reordered with
- * respect to writes, use a dummy memory operand.
- */
-
-#define __FORCE_ORDER "m"(*(unsigned int *)0x1000UL)
-
 void native_write_cr0(unsigned long val);
 
 static inline unsigned long native_read_cr0(void)
 {
        unsigned long val;
-       asm volatile("mov %%cr0,%0\n\t" : "=r" (val) : __FORCE_ORDER);
+       asm volatile("mov %%cr0,%0" : "=r" (val));
        return val;
 }
 
 static __always_inline unsigned long native_read_cr2(void)
 {
        unsigned long val;
-       asm volatile("mov %%cr2,%0\n\t" : "=r" (val) : __FORCE_ORDER);
+       asm volatile("mov %%cr2,%0" : "=r" (val));
        return val;
 }
 
@@ -45,7 +34,7 @@ static __always_inline void native_write_cr2(unsigned long val)
 static __always_inline unsigned long __native_read_cr3(void)
 {
        unsigned long val;
-       asm volatile("mov %%cr3,%0\n\t" : "=r" (val) : __FORCE_ORDER);
+       asm volatile("mov %%cr3,%0" : "=r" (val));
        return val;
 }
 
@@ -66,10 +55,10 @@ static inline unsigned long native_read_cr4(void)
        asm volatile("1: mov %%cr4, %0\n"
                     "2:\n"
                     _ASM_EXTABLE(1b, 2b)
-                    : "=r" (val) : "0" (0), __FORCE_ORDER);
+                    : "=r" (val) : "0" (0));
 #else
        /* CR4 always exists on x86_64. */
-       asm volatile("mov %%cr4,%0\n\t" : "=r" (val) : __FORCE_ORDER);
+       asm volatile("mov %%cr4,%0" : "=r" (val));
 #endif
        return val;
 }