drm/i915/psr: Add new function for writing sink panel replay enable bit
authorJouni Högander <jouni.hogander@intel.com>
Thu, 9 Jan 2025 10:35:29 +0000 (12:35 +0200)
committerJouni Högander <jouni.hogander@intel.com>
Tue, 21 Jan 2025 09:55:34 +0000 (11:55 +0200)
According to DP/eDP specification only DP_PANEL_REPLAY_ENABLE has to be set
prior link training. For this purpose add a new function which sets this
bit on sink side if Panel Replay is supported by the sink and the source.

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250109103532.2093356-2-jouni.hogander@intel.com
drivers/gpu/drm/i915/display/intel_psr.c
drivers/gpu/drm/i915/display/intel_psr.h

index 0b021acb330f476b25874c9601dcb479879c56f8..266b811bd83900d52578d81fb2842c9f79dd2c3d 100644 (file)
@@ -827,6 +827,13 @@ void intel_psr_enable_sink(struct intel_dp *intel_dp,
                drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0);
 }
 
+void intel_psr_panel_replay_enable_sink(struct intel_dp *intel_dp)
+{
+       if (CAN_PANEL_REPLAY(intel_dp))
+               drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG,
+                                  DP_PANEL_REPLAY_ENABLE);
+}
+
 static u32 intel_psr1_get_tp_time(struct intel_dp *intel_dp)
 {
        struct intel_display *display = to_intel_display(intel_dp);
index 956be263c09e396444860837629a9c5b1e4d9683..3b2643b83e0619e0bffe4872b82a276535dd044e 100644 (file)
@@ -30,6 +30,7 @@ bool intel_psr_needs_aux_io_power(struct intel_encoder *encoder,
 void intel_psr_init_dpcd(struct intel_dp *intel_dp);
 void intel_psr_enable_sink(struct intel_dp *intel_dp,
                           const struct intel_crtc_state *crtc_state);
+void intel_psr_panel_replay_enable_sink(struct intel_dp *intel_dp);
 void intel_psr_pre_plane_update(struct intel_atomic_state *state,
                                struct intel_crtc *crtc);
 void intel_psr_post_plane_update(struct intel_atomic_state *state,