drm/amdgpu: enable GFX-V11 userqueue support

This patch enables GFX-v11 IP support in the usermode queue base
code. It typically:
- adds a GFX_v11 specific MQD structure
- sets IP functions to create and destroy MQDs
- sets MQD objects coming from userspace

V10: introduced this spearate patch for GFX V11 enabling (Alex).
V11: Addressed review comments:
     - update the comments in GFX mqd structure informing user about using
       the INFO IOCTL for object sizes (Alex)
     - rename struct drm_amdgpu_userq_mqd_gfx_v11 to
       drm_amdgpu_userq_mqd_gfx11 (Marek)

Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: Christian Koenig <christian.koenig@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Shashank Sharma <shashank.sharma@amd.com>
Signed-off-by: Arvind Yadav <arvind.yadav@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c
index 64a063ec3b27e6b83b373d0e8f2642a52a996db7..5cb984c509c2fc8e927d1c9430d7aeddca52a951 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c
@@ -188,6 +188,12 @@ amdgpu_userqueue_create(struct drm_file *filp, union drm_amdgpu_userq *args)
        uint64_t index;
        int qid, r = 0;
 
+       /* Usermode queues are only supported for GFX IP as of now */
+       if (args->in.ip_type != AMDGPU_HW_IP_GFX) {
+               DRM_ERROR("Usermode queue doesn't support IP type %u\n", args->in.ip_type);
+               return -EINVAL;
+       }
+
        if (args->in.flags) {
                DRM_ERROR("Usermode queue flags not supported yet\n");
                return -EINVAL;

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
index 77df4452979bd1fed6fb427e337d198d00e65e15..ec487fbeaec56f6090c9665c74a361fef0bd18f0 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
@@ -48,6 +48,7 @@
 #include "gfx_v11_0_3.h"
 #include "nbio_v4_3.h"
 #include "mes_v11_0.h"
+#include "mes_v11_0_userqueue.h"
 
 #define GFX11_NUM_GFX_RINGS            1
 #define GFX11_MEC_HPD_SIZE     2048
@@ -1613,6 +1614,7 @@ static int gfx_v11_0_sw_init(struct amdgpu_ip_block *ip_block)
                adev->gfx.mec.num_mec = 1;
                adev->gfx.mec.num_pipe_per_mec = 4;
                adev->gfx.mec.num_queue_per_pipe = 4;
+               adev->userq_funcs[AMDGPU_HW_IP_GFX] = &userq_mes_v11_0_funcs;
                break;
        case IP_VERSION(11, 0, 1):
        case IP_VERSION(11, 0, 4):
@@ -1626,6 +1628,7 @@ static int gfx_v11_0_sw_init(struct amdgpu_ip_block *ip_block)
                adev->gfx.mec.num_mec = 1;
                adev->gfx.mec.num_pipe_per_mec = 4;
                adev->gfx.mec.num_queue_per_pipe = 4;
+               adev->userq_funcs[AMDGPU_HW_IP_GFX] = &userq_mes_v11_0_funcs;
                break;
        default:
                adev->gfx.me.num_me = 1;

diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0_userqueue.c b/drivers/gpu/drm/amd/amdgpu/mes_v11_0_userqueue.c
index bc9ce5233a7d3ffb045151c0a95bd3a4a1b47faa..bcfa0d1ef7bf223309806a95e20e6bc4f6eb9dc4 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0_userqueue.c
+++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0_userqueue.c
@@ -180,6 +180,34 @@ static int mes_v11_0_userq_create_ctx_space(struct amdgpu_userq_mgr *uq_mgr,
                return r;
        }
 
+       /* Shadow, GDS and CSA objects come directly from userspace */
+       if (mqd_user->ip_type == AMDGPU_HW_IP_GFX) {
+               struct v11_gfx_mqd *mqd = queue->mqd.cpu_ptr;
+               struct drm_amdgpu_userq_mqd_gfx11 *mqd_gfx_v11;
+
+               if (mqd_user->mqd_size != sizeof(*mqd_gfx_v11) || !mqd_user->mqd) {
+                       DRM_ERROR("Invalid GFX MQD\n");
+                       return -EINVAL;
+               }
+
+               mqd_gfx_v11 = memdup_user(u64_to_user_ptr(mqd_user->mqd), mqd_user->mqd_size);
+               if (IS_ERR(mqd_gfx_v11)) {
+                       DRM_ERROR("Failed to read user MQD\n");
+                       amdgpu_userqueue_destroy_object(uq_mgr, ctx);
+                       return -ENOMEM;
+               }
+
+               mqd->shadow_base_lo = mqd_gfx_v11->shadow_va & 0xFFFFFFFC;
+               mqd->shadow_base_hi = upper_32_bits(mqd_gfx_v11->shadow_va);
+
+               mqd->gds_bkup_base_lo = mqd_gfx_v11->gds_va & 0xFFFFFFFC;
+               mqd->gds_bkup_base_hi = upper_32_bits(mqd_gfx_v11->gds_va);
+
+               mqd->fw_work_area_base_lo = mqd_gfx_v11->csa_va & 0xFFFFFFFC;
+               mqd->fw_work_area_base_hi = upper_32_bits(mqd_gfx_v11->csa_va);
+               kfree(mqd_gfx_v11);
+       }
+
        return 0;
 }
 

diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
index 53081050cb3eaa0593bbd4a3695df59d10fa1c47..4e07e15d5076c1d61c3e72d2304a9d651bb0c60d 100644 (file)
--- a/include/uapi/drm/amdgpu_drm.h
+++ b/include/uapi/drm/amdgpu_drm.h
@@ -409,6 +409,25 @@ union drm_amdgpu_userq {
        struct drm_amdgpu_userq_out out;
 };
 
+/* GFX V11 IP specific MQD parameters */
+struct drm_amdgpu_userq_mqd_gfx11 {
+       /**
+        * @shadow_va: Virtual address of the GPU memory to hold the shadow buffer.
+        * Use AMDGPU_INFO_IOCTL to find the exact size of the object.
+        */
+       __u64   shadow_va;
+       /**
+        * @gds_va: Virtual address of the GPU memory to hold the GDS buffer.
+        * Use AMDGPU_INFO_IOCTL to find the exact size of the object.
+        */
+       __u64   gds_va;
+       /**
+        * @csa_va: Virtual address of the GPU memory to hold the CSA buffer.
+        * Use AMDGPU_INFO_IOCTL to find the exact size of the object.
+        */
+       __u64   csa_va;
+};
+
 /* vm ioctl */
 #define AMDGPU_VM_OP_RESERVE_VMID      1
 #define AMDGPU_VM_OP_UNRESERVE_VMID    2