clk: renesas: r9a07g044: Add clock and reset entry for SCI1

Add clock and reset entry for SCI1 interface.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20211103160537.32253-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c
index 47c16265fca9ebae8e1d58f39f742ea6beaccca2..463b658a0c5421958d3d0278f2d805a5bc1d72b1 100644 (file)
--- a/drivers/clk/renesas/r9a07g044-cpg.c
+++ b/drivers/clk/renesas/r9a07g044-cpg.c
@@ -217,6 +217,8 @@ static struct rzg2l_mod_clk r9a07g044_mod_clks[] = {
                                0x584, 4),
        DEF_MOD("sci0",         R9A07G044_SCI0_CLKP, R9A07G044_CLK_P0,
                                0x588, 0),
+       DEF_MOD("sci1",         R9A07G044_SCI1_CLKP, R9A07G044_CLK_P0,
+                               0x588, 1),
        DEF_MOD("canfd",        R9A07G044_CANFD_PCLK, R9A07G044_CLK_P0,
                                0x594, 0),
        DEF_MOD("gpio",         R9A07G044_GPIO_HCLK, R9A07G044_OSCCLK,
@@ -256,6 +258,7 @@ static struct rzg2l_reset r9a07g044_resets[] = {
        DEF_RST(R9A07G044_SCIF3_RST_SYSTEM_N, 0x884, 3),
        DEF_RST(R9A07G044_SCIF4_RST_SYSTEM_N, 0x884, 4),
        DEF_RST(R9A07G044_SCI0_RST, 0x888, 0),
+       DEF_RST(R9A07G044_SCI1_RST, 0x888, 1),
        DEF_RST(R9A07G044_CANFD_RSTP_N, 0x894, 0),
        DEF_RST(R9A07G044_CANFD_RSTC_N, 0x894, 1),
        DEF_RST(R9A07G044_GPIO_RSTN, 0x898, 0),