drm/i915/chv: Implement WaDisableShadowRegForCpd
authorDeepak S <deepak.s@linux.intel.com>
Thu, 16 Apr 2015 03:21:28 +0000 (08:51 +0530)
committerJani Nikula <jani.nikula@intel.com>
Tue, 28 Apr 2015 14:31:29 +0000 (17:31 +0300)
This WA is avoid problem between shadow vs wake FIFO unload
problem during CPD/RC6 transactions on CHV.

v2: Define individual bits GTFIFOCTL (Ville)

v3: move WA to uncore_early_sanitize (ville)

Signed-off-by: Deepak S <deepak.s@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
[Jani: fixed some whitespace issues while applying]
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
drivers/gpu/drm/i915/i915_reg.h
drivers/gpu/drm/i915/intel_uncore.c

index 3da1af46625c73a5a24c996b56e94c6f0b637526..773d1d24e604ccc74b92552d07264bb1b3991938 100644 (file)
@@ -6074,6 +6074,8 @@ enum skl_disp_power_wells {
 #define  GTFIFOCTL                             0x120008
 #define    GT_FIFO_FREE_ENTRIES_MASK           0x7f
 #define    GT_FIFO_NUM_RESERVED_ENTRIES                20
+#define    GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL  (1 << 12)
+#define    GT_FIFO_CTL_RC6_POLICY_STALL                (1 << 11)
 
 #define  HSW_IDICR                             0x9008
 #define    IDIHASHMSK(x)                       (((x) & 0x3f) << 16)
index ab5cc94588e10d1ac1ac81e3330073ea92d17ac7..ff2a74651dd48561c0170427ca9b89f3db54c9d4 100644 (file)
@@ -360,6 +360,14 @@ static void __intel_uncore_early_sanitize(struct drm_device *dev,
                __raw_i915_write32(dev_priv, GTFIFODBG,
                                   __raw_i915_read32(dev_priv, GTFIFODBG));
 
+       /* WaDisableShadowRegForCpd:chv */
+       if (IS_CHERRYVIEW(dev)) {
+               __raw_i915_write32(dev_priv, GTFIFOCTL,
+                                  __raw_i915_read32(dev_priv, GTFIFOCTL) |
+                                  GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL |
+                                  GT_FIFO_CTL_RC6_POLICY_STALL);
+       }
+
        intel_uncore_forcewake_reset(dev, restore_forcewake);
 }