selftests/powerpc: Fixup clobbers for TM tests
authorMichael Ellerman <mpe@ellerman.id.au>
Mon, 14 Oct 2019 02:30:43 +0000 (13:30 +1100)
committerMichael Ellerman <mpe@ellerman.id.au>
Tue, 29 Oct 2019 09:53:49 +0000 (20:53 +1100)
Some of our TM (Transactional Memory) tests, list "r1" (the stack
pointer) as a clobbered register.

GCC >= 9 doesn't accept this, and the build breaks:

  ptrace-tm-spd-tar.c: In function 'tm_spd_tar':
  ptrace-tm-spd-tar.c:31:2: error: listing the stack pointer register 'r1' in a clobber list is deprecated [-Werror=deprecated]
     31 |  asm __volatile__(
        |  ^~~
  ptrace-tm-spd-tar.c:31:2: note: the value of the stack pointer after an 'asm' statement must be the same as it was before the statement

We do have some fairly large inline asm blocks in these tests, and
some of them do change the value of r1. However they should all return
to C with the value in r1 restored, so I think it's legitimate to say
r1 is not clobbered.

As Segher points out, the r1 clobbers may have been added because of
the use of `or 1,1,1`, however that doesn't actually clobber r1.

Segher also points out that some of these tests do clobber LR, because
they call functions, and that is not listed in the clobbers, so add
that where appropriate.

Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20191029095324.14669-1-mpe@ellerman.id.au
tools/testing/selftests/powerpc/ptrace/ptrace-tm-spd-tar.c
tools/testing/selftests/powerpc/ptrace/ptrace-tm-spd-vsx.c
tools/testing/selftests/powerpc/ptrace/ptrace-tm-tar.c
tools/testing/selftests/powerpc/ptrace/ptrace-tm-vsx.c

index 25e23e73c72e6c709fe3f53552a35b445f57f5b6..2ecfa1158e2bcf5e8c2c9a259f615f8de59737f0 100644 (file)
@@ -73,7 +73,7 @@ trans:
                [sprn_texasr]"i"(SPRN_TEXASR), [tar_1]"i"(TAR_1),
                [dscr_1]"i"(DSCR_1), [tar_2]"i"(TAR_2), [dscr_2]"i"(DSCR_2),
                [tar_3]"i"(TAR_3), [dscr_3]"i"(DSCR_3)
-               : "memory", "r0", "r1", "r3", "r4", "r5", "r6"
+               : "memory", "r0", "r3", "r4", "r5", "r6", "lr"
                );
 
        /* TM failed, analyse */
index f603fe5a445b3fc6648bce5bd11a71e73440a935..6f7fb51f08099ccc1f47069a78a25d3a2d8ccf1a 100644 (file)
@@ -74,8 +74,8 @@ trans:
                "3: ;"
                : [res] "=r" (result), [texasr] "=r" (texasr)
                : [sprn_texasr] "i"  (SPRN_TEXASR)
-               : "memory", "r0", "r1", "r3", "r4",
-               "r7", "r8", "r9", "r10", "r11"
+               : "memory", "r0", "r3", "r4",
+                 "r7", "r8", "r9", "r10", "r11", "lr"
                );
 
        if (result) {
index e0d37f07bdeba44c61a7ec9ab4109abd26a30f32..46ef378a15ecc6c829de2f68e5a3f6d945b7c42f 100644 (file)
@@ -62,7 +62,7 @@ trans:
                [sprn_ppr]"i"(SPRN_PPR), [sprn_texasr]"i"(SPRN_TEXASR),
                [tar_1]"i"(TAR_1), [dscr_1]"i"(DSCR_1), [tar_2]"i"(TAR_2),
                [dscr_2]"i"(DSCR_2), [cptr1] "b" (&cptr[1])
-               : "memory", "r0", "r1", "r3", "r4", "r5", "r6"
+               : "memory", "r0", "r3", "r4", "r5", "r6"
                );
 
        /* TM failed, analyse */
index 8027457b97b7c983e4ac2b03c6e9be3ec63f7931..70ca01234f79c4f54cfc41d232c701effb181b8f 100644 (file)
@@ -62,8 +62,8 @@ trans:
                "3: ;"
                : [res] "=r" (result), [texasr] "=r" (texasr)
                : [sprn_texasr] "i"  (SPRN_TEXASR), [cptr1] "b" (&cptr[1])
-               : "memory", "r0", "r1", "r3", "r4",
-               "r7", "r8", "r9", "r10", "r11"
+               : "memory", "r0", "r3", "r4",
+                 "r7", "r8", "r9", "r10", "r11", "lr"
                );
 
        if (result) {