{
struct r8192_priv *priv = rtllib_priv(dev);
u8 powerlevel = 0, powerlevelOFDM24G = 0;
- u32 u4RegValue;
if (priv->epromtype == EEPROM_93C46) {
powerlevel = priv->tx_pwr_level_cck[channel - 1];
priv->antenna_tx_pwr_diff[1] = 0;
priv->antenna_tx_pwr_diff[0] = 0;
- u4RegValue = priv->antenna_tx_pwr_diff[2] << 8 |
- priv->antenna_tx_pwr_diff[1] << 4 |
- priv->antenna_tx_pwr_diff[0];
-
rtl92e_set_bb_reg(dev, rFPGA0_TxGainStage,
- (bXBTxAGC|bXCTxAGC|bXDTxAGC),
- u4RegValue);
+ (bXBTxAGC | bXCTxAGC | bXDTxAGC), 0);
}
}
switch (priv->rf_chip) {