dt-bindings: memory: snps,dw-umctl2-ddrc: Use more descriptive device name

The DT-schema name and the corresponding generic compatible string look
inappropriate in the current DW uMCTL2 DDRC DT-bindings:
1. DT-schema name contains undefined vendor-prefix. It's supposed to be
"snps", not "synopsys".
2. DT-schema name has "ecc" suffix. That is a device property, and has
nothing to do with the controller actual name.
3. The controller name is different. It's DW uMCTL2 DDRC. Just DDRC
doesn't identify the IP-core in subject.
4. There is no much point in using the IP-core version in the device name
since it can be retrieved from the corresponding device CSR. Moreover the
DW uMCTL2 DDRC driver doesn't differentiate the IP-core version at the
current state.

In order to fix all the inconsistencies described above we suggest to
rename the DT-schema to "snps,dw-umctl2-ddrc.yaml", deprecate the
compatible string "snps,ddrc-3.80a" and define a new generic device
name as "snps,dw-umctl2-ddrc".

Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220910194237.10142-16-Sergey.Semin@baikalelectronics.ru

diff --git a/Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml b/Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml
new file mode 100644 (file)
index 0000000..9212dfe
--- /dev/null
+++ b/Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml
@@ -0,0 +1,56 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/memory-controllers/snps,dw-umctl2-ddrc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Synopsys DesignWare Universal Multi-Protocol Memory Controller
+
+maintainers:
+  - Krzysztof Kozlowski <krzk@kernel.org>
+  - Manish Narani <manish.narani@xilinx.com>
+  - Michal Simek <michal.simek@xilinx.com>
+
+description: |
+  Synopsys DesignWare Enhanced uMCTL2 DDR Memory Controller is capable of
+  working with the memory devices supporting up to (LP)DDR4 protocol. It can
+  be equipped with SEC/DEC ECC feature if DRAM data bus width is either
+  16-bits or 32-bits or 64-bits wide.
+
+  For instance the ZynqMP DDR controller is based on the DW uMCTL2 v2.40a
+  controller. It has an optional SEC/DEC ECC support in 64- and 32-bits
+  bus width configurations.
+
+properties:
+  compatible:
+    oneOf:
+      - deprecated: true
+        description: Synopsys DW uMCTL2 DDR controller v3.80a
+        const: snps,ddrc-3.80a
+      - description: Synopsys DW uMCTL2 DDR controller
+        const: snps,dw-umctl2-ddrc
+      - description: Xilinx ZynqMP DDR controller v2.40a
+        const: xlnx,zynqmp-ddrc-2.40a
+
+  interrupts:
+    maxItems: 1
+
+  reg:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - interrupts
+
+additionalProperties: false
+
+examples:
+  - |
+    memory-controller@fd070000 {
+      compatible = "xlnx,zynqmp-ddrc-2.40a";
+      reg = <0xfd070000 0x30000>;
+      interrupt-parent = <&gic>;
+      interrupts = <0 112 4>;
+    };
+...

diff --git a/Documentation/devicetree/bindings/memory-controllers/synopsys,ddrc-ecc.yaml b/Documentation/devicetree/bindings/memory-controllers/synopsys,ddrc-ecc.yaml
deleted file mode 100644 (file)
index 0be8ecc..0000000
--- a/Documentation/devicetree/bindings/memory-controllers/synopsys,ddrc-ecc.yaml
+++ /dev/null
@@ -1,53 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/memory-controllers/synopsys,ddrc-ecc.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: Synopsys DesignWare Universal Multi-Protocol Memory Controller
-
-maintainers:
-  - Krzysztof Kozlowski <krzk@kernel.org>
-  - Manish Narani <manish.narani@xilinx.com>
-  - Michal Simek <michal.simek@xilinx.com>
-
-description: |
-  Synopsys DesignWare Enhanced uMCTL2 DDR Memory Controller is capable of
-  working with the memory devices supporting up to (LP)DDR4 protocol. It can
-  be equipped with SEC/DEC ECC feature if DRAM data bus width is either
-  16-bits or 32-bits or 64-bits wide.
-
-  For instance the ZynqMP DDR controller is based on the DW uMCTL2 v2.40a
-  controller. It has an optional SEC/DEC ECC support in 64- and 32-bits
-  bus width configurations.
-
-properties:
-  compatible:
-    oneOf:
-      - description: Synopsys DW uMCTL2 DDR controller v3.80a
-        const: snps,ddrc-3.80a
-      - description: Xilinx ZynqMP DDR controller v2.40a
-        const: xlnx,zynqmp-ddrc-2.40a
-
-  interrupts:
-    maxItems: 1
-
-  reg:
-    maxItems: 1
-
-required:
-  - compatible
-  - reg
-  - interrupts
-
-additionalProperties: false
-
-examples:
-  - |
-    memory-controller@fd070000 {
-      compatible = "xlnx,zynqmp-ddrc-2.40a";
-      reg = <0xfd070000 0x30000>;
-      interrupt-parent = <&gic>;
-      interrupts = <0 112 4>;
-    };
-...

diff --git a/MAINTAINERS b/MAINTAINERS
index 1d51bdb5143ebaac528a081b0cf3c3727c9dde1b..7b271489819894003d5f063927dadfb84e5704ea 100644 (file)
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -3087,6 +3087,7 @@ W:        http://wiki.xilinx.com
 T:     git https://github.com/Xilinx/linux-xlnx.git
 F:     Documentation/devicetree/bindings/i2c/cdns,i2c-r1p10.yaml
 F:     Documentation/devicetree/bindings/i2c/xlnx,xps-iic-2.00.a.yaml
+F:     Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml
 F:     Documentation/devicetree/bindings/memory-controllers/xlnx,zynq-ddrc-a05.yaml
 F:     Documentation/devicetree/bindings/spi/xlnx,zynq-qspi.yaml
 F:     arch/arm/mach-zynq/