arm64: dts: rockchip: add rk356x dwc3 usb3 nodes
authorPeter Geis <pgwipeout@gmail.com>
Fri, 8 Apr 2022 15:12:35 +0000 (11:12 -0400)
committerHeiko Stuebner <heiko@sntech.de>
Sun, 10 Apr 2022 16:45:08 +0000 (18:45 +0200)
Add the dwc3 device nodes to the rk356x device trees.
The rk3566 has one usb2 capable dwc3 otg controller and one usb3 capable
dwc3 host controller.
The rk3568 has one usb3 capable dwc3 otg controller and one usb3 capable
dwc3 host controller.

Signed-off-by: Peter Geis <pgwipeout@gmail.com>
Tested-by: Frank Wunderlich <frank-w@public-files.de>
Link: https://lore.kernel.org/r/20220408151237.3165046-4-pgwipeout@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
arch/arm64/boot/dts/rockchip/rk3566.dtsi
arch/arm64/boot/dts/rockchip/rk3568.dtsi
arch/arm64/boot/dts/rockchip/rk356x.dtsi

index 3839eef5e4f76ace7347822b036f671bc25841e7..0b957068ff8991c6003da13fbd09bc63bb705e6f 100644 (file)
@@ -6,6 +6,10 @@
        compatible = "rockchip,rk3566";
 };
 
+&pipegrf {
+       compatible = "rockchip,rk3566-pipe-grf", "syscon";
+};
+
 &power {
        power-domain@RK3568_PD_PIPE {
                reg = <RK3568_PD_PIPE>;
                #power-domain-cells = <0>;
        };
 };
+
+&usb_host0_xhci {
+       phys = <&usb2phy0_otg>;
+       phy-names = "usb2-phy";
+       extcon = <&usb2phy0>;
+       maximum-speed = "high-speed";
+};
index 3e07d9f6a2d129fe679be28103efe8858c8de2c2..5eafddf62edc786d82697abc213d0943a67336e6 100644 (file)
        };
 };
 
+&pipegrf {
+       compatible = "rockchip,rk3568-pipe-grf", "syscon";
+};
+
 &power {
        power-domain@RK3568_PD_PIPE {
                reg = <RK3568_PD_PIPE>;
                #power-domain-cells = <0>;
        };
 };
+
+&usb_host0_xhci {
+       phys = <&usb2phy0_otg>, <&combphy0 PHY_TYPE_USB3>;
+       phy-names = "usb2-phy", "usb3-phy";
+};
index 264dd030e7032ac890192eb8f51a1f1d1d0325ed..55e6dcb948cc502ecb34e367ae86c8818a2af577 100644 (file)
                status = "disabled";
        };
 
+       usb_host0_xhci: usb@fcc00000 {
+               compatible = "rockchip,rk3568-dwc3", "snps,dwc3";
+               reg = <0x0 0xfcc00000 0x0 0x400000>;
+               interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cru CLK_USB3OTG0_REF>, <&cru CLK_USB3OTG0_SUSPEND>,
+                        <&cru ACLK_USB3OTG0>;
+               clock-names = "ref_clk", "suspend_clk",
+                             "bus_clk";
+               dr_mode = "host";
+               phy_type = "utmi_wide";
+               power-domains = <&power RK3568_PD_PIPE>;
+               resets = <&cru SRST_USB3OTG0>;
+               snps,dis_u2_susphy_quirk;
+               status = "disabled";
+       };
+
+       usb_host1_xhci: usb@fd000000 {
+               compatible = "rockchip,rk3568-dwc3", "snps,dwc3";
+               reg = <0x0 0xfd000000 0x0 0x400000>;
+               interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cru CLK_USB3OTG1_REF>, <&cru CLK_USB3OTG1_SUSPEND>,
+                        <&cru ACLK_USB3OTG1>;
+               clock-names = "ref_clk", "suspend_clk",
+                             "bus_clk";
+               dr_mode = "host";
+               phys = <&usb2phy0_host>, <&combphy1 PHY_TYPE_USB3>;
+               phy-names = "usb2-phy", "usb3-phy";
+               phy_type = "utmi_wide";
+               power-domains = <&power RK3568_PD_PIPE>;
+               resets = <&cru SRST_USB3OTG1>;
+               snps,dis_u2_susphy_quirk;
+               status = "disabled";
+       };
+
        gic: interrupt-controller@fd400000 {
                compatible = "arm,gic-v3";
                reg = <0x0 0xfd400000 0 0x10000>, /* GICD */
        };
 
        pipegrf: syscon@fdc50000 {
-               compatible = "rockchip,rk3568-pipe-grf", "syscon";
                reg = <0x0 0xfdc50000 0x0 0x1000>;
        };