usb: typec: tcpm/tcpci_maxim: use GENMASK() for TCPC_VENDOR_CC_CTRL2 register
authorAndré Draszik <andre.draszik@linaro.org>
Wed, 10 Jul 2024 10:36:18 +0000 (11:36 +0100)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Wed, 7 Aug 2024 10:49:30 +0000 (12:49 +0200)
Convert register TCPC_VENDOR_CC_CTRL2 to using GENMASK() and
FIELD_PREP() so as to keep using a similar approach throughout the code
base and make it arguably easier to read.

Signed-off-by: André Draszik <andre.draszik@linaro.org>
Reviewed-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
Link: https://lore.kernel.org/r/20240710-tcpc-cleanup-v1-11-0ec1f41f4263@linaro.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
drivers/usb/typec/tcpm/maxim_contaminant.c
drivers/usb/typec/tcpm/tcpci_maxim.h

index 8ac8eeade27744b994c32d0cfbd9c0620b623b67..f7acaa42329f750502c9089398e72431b1e2d942 100644 (file)
@@ -116,13 +116,14 @@ static int max_contaminant_read_resistance_kohm(struct max_tcpci_chip *chip,
        if (channel == CC1_SCALE1 || channel == CC2_SCALE1 || channel == CC1_SCALE2 ||
            channel == CC2_SCALE2) {
                /* Enable 1uA current source */
-               ret = regmap_update_bits(regmap, TCPC_VENDOR_CC_CTRL2, CCLPMODESEL_MASK,
-                                        ULTRA_LOW_POWER_MODE);
+               ret = regmap_update_bits(regmap, TCPC_VENDOR_CC_CTRL2, CCLPMODESEL,
+                                        FIELD_PREP(CCLPMODESEL, ULTRA_LOW_POWER_MODE));
                if (ret < 0)
                        return ret;
 
                /* Enable 1uA current source */
-               ret = regmap_update_bits(regmap, TCPC_VENDOR_CC_CTRL2, CCRPCTRL_MASK, UA_1_SRC);
+               ret = regmap_update_bits(regmap, TCPC_VENDOR_CC_CTRL2, CCRPCTRL,
+                                        FIELD_PREP(CCRPCTRL, UA_1_SRC));
                if (ret < 0)
                        return ret;
 
@@ -176,7 +177,8 @@ static int max_contaminant_read_comparators(struct max_tcpci_chip *chip, u8 *ven
        int ret;
 
        /* Enable 80uA source */
-       ret = regmap_update_bits(regmap, TCPC_VENDOR_CC_CTRL2, CCRPCTRL_MASK, UA_80_SRC);
+       ret = regmap_update_bits(regmap, TCPC_VENDOR_CC_CTRL2, CCRPCTRL,
+                                FIELD_PREP(CCRPCTRL, UA_80_SRC));
        if (ret < 0)
                return ret;
 
@@ -209,7 +211,8 @@ static int max_contaminant_read_comparators(struct max_tcpci_chip *chip, u8 *ven
        if (ret < 0)
                return ret;
 
-       ret = regmap_update_bits(regmap, TCPC_VENDOR_CC_CTRL2, CCRPCTRL_MASK, 0);
+       ret = regmap_update_bits(regmap, TCPC_VENDOR_CC_CTRL2, CCRPCTRL,
+                                FIELD_PREP(CCRPCTRL, 0));
        if (ret < 0)
                return ret;
 
@@ -298,8 +301,9 @@ static int max_contaminant_enable_dry_detection(struct max_tcpci_chip *chip)
        if (ret < 0)
                return ret;
 
-       ret = regmap_update_bits(regmap, TCPC_VENDOR_CC_CTRL2, CCLPMODESEL_MASK,
-                                ULTRA_LOW_POWER_MODE);
+       ret = regmap_update_bits(regmap, TCPC_VENDOR_CC_CTRL2, CCLPMODESEL,
+                                FIELD_PREP(CCLPMODESEL,
+                                           ULTRA_LOW_POWER_MODE));
        if (ret < 0)
                return ret;
        ret = max_tcpci_read8(chip, TCPC_VENDOR_CC_CTRL2, &temp);
index 78ff3b73ee7e3c623386ecd35264454ab857c15a..92c9a628ebe181eb8f720ef76c0dff132f5146a6 100644 (file)
@@ -20,9 +20,9 @@
 #define SBUOVPDIS                               BIT(7)
 #define CCOVPDIS                                BIT(6)
 #define SBURPCTRL                               BIT(5)
-#define CCLPMODESEL_MASK                        GENMASK(4, 3)
-#define ULTRA_LOW_POWER_MODE                    BIT(3)
-#define CCRPCTRL_MASK                           GENMASK(2, 0)
+#define CCLPMODESEL                             GENMASK(4, 3)
+#define ULTRA_LOW_POWER_MODE                    1
+#define CCRPCTRL                                GENMASK(2, 0)
 #define UA_1_SRC                                1
 #define UA_80_SRC                               3