arm64: dts: qcom: x1e80100: Resize GIC Redistributor register region

Resize the GICR register region as it currently seeps into the CPU Control
Processor mailbox RX region.

Fixes: af16b00578a7 ("arm64: dts: qcom: Add base X1E80100 dtsi and the QCP dts")
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com>
Link: https://lore.kernel.org/r/20240612124056.39230-4-quic_sibis@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
index f3fb527c0b0888e335b33e55f0f90a5ab57dcc69..a85a7bdfbf5260110bd32fd4364f46927b2b2ff5 100644 (file)
--- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
+++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
@@ -5754,7 +5754,7 @@
                intc: interrupt-controller@17000000 {
                        compatible = "arm,gic-v3";
                        reg = <0 0x17000000 0 0x10000>,     /* GICD */
-                             <0 0x17080000 0 0x480000>;    /* GICR * 12 */
+                             <0 0x17080000 0 0x300000>;    /* GICR * 12 */
 
                        interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;