drm/amdgpu: add the support of XGMI link for GC 9.4.3

Add the xgmi LFB_CNTL/LBF_SIZE reg addresses to fetch the xgmi info from.

v2: move get_xgmi_info() to GC_V9_4_3 sepecific source files to utilize
the register definitions specific for GC_V9_4_3
v3: remove the duplicated register definitions
v4: enable xgmi based on asic_type as XGMI_IP ver is not available
yet for IP discovery

Signed-off-by: Shiwu Zhang <shiwu.zhang@amd.com>
Reviewed-by: Le Ma <Le.Ma@amd.com>
Ack-by: Lijo Lazar <Lijo.Lazar@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c
index d3424ce97aa8945ae936f7c9b68401684c25ed3c..1bb17d95f7208b3c78c7c9ddb63e0d38c8517cef 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c
@@ -528,6 +528,45 @@ static void gfxhub_v1_2_init(struct amdgpu_device *adev)
        }
 }
 
+static int gfxhub_v1_2_get_xgmi_info(struct amdgpu_device *adev)
+{
+       u32 max_num_physical_nodes;
+       u32 max_physical_node_id;
+       u32 xgmi_lfb_cntl;
+       u32 max_region;
+       u64 seg_size;
+
+       xgmi_lfb_cntl = RREG32_SOC15(GC, 0, regMC_VM_XGMI_LFB_CNTL);
+       seg_size = REG_GET_FIELD(
+               RREG32_SOC15(GC, 0, regMC_VM_XGMI_LFB_SIZE),
+               MC_VM_XGMI_LFB_SIZE, PF_LFB_SIZE) << 24;
+       max_region =
+               REG_GET_FIELD(xgmi_lfb_cntl, MC_VM_XGMI_LFB_CNTL, PF_MAX_REGION);
+
+
+
+       max_num_physical_nodes   = 8;
+       max_physical_node_id     = 7;
+
+       /* PF_MAX_REGION=0 means xgmi is disabled */
+       if (max_region || adev->gmc.xgmi.connected_to_cpu) {
+               adev->gmc.xgmi.num_physical_nodes = max_region + 1;
+
+               if (adev->gmc.xgmi.num_physical_nodes > max_num_physical_nodes)
+                       return -EINVAL;
+
+               adev->gmc.xgmi.physical_node_id =
+                       REG_GET_FIELD(xgmi_lfb_cntl, MC_VM_XGMI_LFB_CNTL,
+                                       PF_LFB_REGION);
+
+               if (adev->gmc.xgmi.physical_node_id > max_physical_node_id)
+                       return -EINVAL;
+
+               adev->gmc.xgmi.node_segment_size = seg_size;
+       }
+
+       return 0;
+}
 
 const struct amdgpu_gfxhub_funcs gfxhub_v1_2_funcs = {
        .get_mc_fb_offset = gfxhub_v1_2_get_mc_fb_offset,
@@ -536,5 +575,5 @@ const struct amdgpu_gfxhub_funcs gfxhub_v1_2_funcs = {
        .gart_disable = gfxhub_v1_2_gart_disable,
        .set_fault_enable_default = gfxhub_v1_2_set_fault_enable_default,
        .init = gfxhub_v1_2_init,
-       .get_xgmi_info = gfxhub_v1_1_get_xgmi_info,
+       .get_xgmi_info = gfxhub_v1_2_get_xgmi_info,
 };

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 59be0c0293c4d4a2f2bb68df0ac440cf4f88fb10..4b2c4ecd725381ee175911fd9876dde84d240951 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -1419,9 +1419,13 @@ static int gmc_v9_0_early_init(void *handle)
 {
        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
-       /* ARCT and VEGA20 don't have XGMI defined in their IP discovery tables */
-       if (adev->asic_type == CHIP_VEGA20 ||
-           adev->asic_type == CHIP_ARCTURUS)
+       /*
+        * 9.4.0, 9.4.1 and 9.4.3 don't have XGMI defined
+        * in their IP discovery tables
+        */
+       if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 0) ||
+           adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 1) ||
+           adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 3))
                adev->gmc.xgmi.supported = true;
 
        if (adev->ip_versions[XGMI_HWIP][0] == IP_VERSION(6, 1, 0)) {