drm/xe: Allow to assign GGTT region to the VF

VF's drivers can't modify GGTT PTEs except the range explicitly
assigned by the PF driver. To allow hardware enforcement of this
requirement, each GGTT PTE has a field with the VF number that
identifies which VF can modify that particular GGTT PTE entry.

Only PF driver can modify this field and PF driver shall do that
before VF drivers will be loaded. Add function to prepare PTEs.
Since it will be used only by the PF driver, make it available
only for CONFIG_PCI_IOV=y.

Bspec: 45015, 52395
Reviewed-by: Piotr Piórkowski <piotr.piorkowski@intel.com>
Reviewed-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240415173937.1287-3-michal.wajdeczko@intel.com

diff --git a/drivers/gpu/drm/xe/regs/xe_gtt_defs.h b/drivers/gpu/drm/xe/regs/xe_gtt_defs.h
index 558519ce48c7fc94fb365af403d9a98aa0aa9248..4389e5a76f896e4a4c75d2ac4759442e193874c4 100644 (file)
--- a/drivers/gpu/drm/xe/regs/xe_gtt_defs.h
+++ b/drivers/gpu/drm/xe/regs/xe_gtt_defs.h
@@ -9,6 +9,8 @@
 #define XELPG_GGTT_PTE_PAT0    BIT_ULL(52)
 #define XELPG_GGTT_PTE_PAT1    BIT_ULL(53)
 
+#define GGTT_PTE_VFID          GENMASK_ULL(11, 2)
+
 #define GUC_GGTT_TOP           0xFEE00000
 
 #define XELPG_PPGTT_PTE_PAT3           BIT_ULL(62)

diff --git a/drivers/gpu/drm/xe/xe_ggtt.c b/drivers/gpu/drm/xe/xe_ggtt.c
index ff2239c0eda53a9212f63734f992d01dd6857a88..f090cab065b84c90d23b0160567696fb910e21a1 100644 (file)
--- a/drivers/gpu/drm/xe/xe_ggtt.c
+++ b/drivers/gpu/drm/xe/xe_ggtt.c
@@ -460,6 +460,50 @@ void xe_ggtt_remove_bo(struct xe_ggtt *ggtt, struct xe_bo *bo)
                            bo->flags & XE_BO_FLAG_GGTT_INVALIDATE);
 }
 
+#ifdef CONFIG_PCI_IOV
+static u64 xe_encode_vfid_pte(u16 vfid)
+{
+       return FIELD_PREP(GGTT_PTE_VFID, vfid) | XE_PAGE_PRESENT;
+}
+
+static void xe_ggtt_assign_locked(struct xe_ggtt *ggtt, const struct drm_mm_node *node, u16 vfid)
+{
+       u64 start = node->start;
+       u64 size = node->size;
+       u64 end = start + size - 1;
+       u64 pte = xe_encode_vfid_pte(vfid);
+
+       lockdep_assert_held(&ggtt->lock);
+
+       if (!drm_mm_node_allocated(node))
+               return;
+
+       while (start < end) {
+               xe_ggtt_set_pte(ggtt, start, pte);
+               start += XE_PAGE_SIZE;
+       }
+
+       xe_ggtt_invalidate(ggtt);
+}
+
+/**
+ * xe_ggtt_assign - assign a GGTT region to the VF
+ * @ggtt: the &xe_ggtt where the node belongs
+ * @node: the &drm_mm_node to update
+ * @vfid: the VF identifier
+ *
+ * This function is used by the PF driver to assign a GGTT region to the VF.
+ * In addition to PTE's VFID bits 11:2 also PRESENT bit 0 is set as on some
+ * platforms VFs can't modify that either.
+ */
+void xe_ggtt_assign(struct xe_ggtt *ggtt, const struct drm_mm_node *node, u16 vfid)
+{
+       mutex_lock(&ggtt->lock);
+       xe_ggtt_assign_locked(ggtt, node, vfid);
+       mutex_unlock(&ggtt->lock);
+}
+#endif
+
 int xe_ggtt_dump(struct xe_ggtt *ggtt, struct drm_printer *p)
 {
        int err;

diff --git a/drivers/gpu/drm/xe/xe_ggtt.h b/drivers/gpu/drm/xe/xe_ggtt.h
index 8306ef74abc6e7aecdbd453bf4e8d5e47856af68..4a41a1762358ac0a0043f7a7c7c3e3ca130a5016 100644 (file)
--- a/drivers/gpu/drm/xe/xe_ggtt.h
+++ b/drivers/gpu/drm/xe/xe_ggtt.h
@@ -33,4 +33,8 @@ void xe_ggtt_remove_bo(struct xe_ggtt *ggtt, struct xe_bo *bo);
 
 int xe_ggtt_dump(struct xe_ggtt *ggtt, struct drm_printer *p);
 
+#ifdef CONFIG_PCI_IOV
+void xe_ggtt_assign(struct xe_ggtt *ggtt, const struct drm_mm_node *node, u16 vfid);
+#endif
+
 #endif