drm/amdgpu/mes: centralize gfx_hqd mask management

Move it to amdgpu_mes to align with the compute and
sdma hqd masks. No functional change.

v2: rebase on new changes
v3: misc optimizations

Reviewed-by: Prike Liang <Prike.Liang@amd.com>
Reviewed-by: Sunil Khatri<sunil.khatri@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
index 1d355b0fd4b6b6be9186b1e628803e539fc0d470..016af4e9c35fadf962baa910caeb18d6dd307db2 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
@@ -108,6 +108,27 @@ int amdgpu_mes_init(struct amdgpu_device *adev)
        adev->mes.vmid_mask_mmhub = 0xffffff00;
        adev->mes.vmid_mask_gfxhub = 0xffffff00;
 
+       for (i = 0; i < AMDGPU_MES_MAX_GFX_PIPES; i++) {
+               if (i >= adev->gfx.me.num_pipe_per_me * adev->gfx.me.num_me)
+                       break;
+               if (amdgpu_ip_version(adev, GC_HWIP, 0) >=
+                   IP_VERSION(12, 0, 0))
+                       /*
+                        * GFX V12 has only one GFX pipe, but 8 queues in it.
+                        * GFX pipe 0 queue 0 is being used by Kernel queue.
+                        * Set GFX pipe 0 queue 1-7 for MES scheduling
+                        * mask = 1111 1110b
+                        */
+                       adev->mes.gfx_hqd_mask[i] = 0xFE;
+               else
+                       /*
+                        * GFX pipe 0 queue 0 is being used by Kernel queue.
+                        * Set GFX pipe 0 queue 1 for MES scheduling
+                        * mask = 10b
+                        */
+                       adev->mes.gfx_hqd_mask[i] = 0x2;
+       }
+
        for (i = 0; i < AMDGPU_MES_MAX_COMPUTE_PIPES; i++) {
                if (i >= (adev->gfx.mec.num_pipe_per_mec * adev->gfx.mec.num_mec))
                        break;

diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
index ccc19a40f03d47a482634e273b2d8f669936ffd4..06b51867c9aace5d837d528e3f5f6f8414a83ca0 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
@@ -669,18 +669,6 @@ static int mes_v11_0_misc_op(struct amdgpu_mes *mes,
                        offsetof(union MESAPI__MISC, api_status));
 }
 
-static void mes_v11_0_set_gfx_hqd_mask(union MESAPI_SET_HW_RESOURCES *pkt)
-{
-       /*
-        * GFX pipe 0 queue 0 is being used by Kernel queue.
-        * Set GFX pipe 0 queue 1 for MES scheduling
-        * mask = 10b
-        * GFX pipe 1 can't be used for MES due to HW limitation.
-        */
-       pkt->gfx_hqd_mask[0] = 0x2;
-       pkt->gfx_hqd_mask[1] = 0;
-}
-
 static int mes_v11_0_set_hw_resources(struct amdgpu_mes *mes)
 {
        int i;
@@ -705,7 +693,9 @@ static int mes_v11_0_set_hw_resources(struct amdgpu_mes *mes)
                mes_set_hw_res_pkt.compute_hqd_mask[i] =
                        mes->compute_hqd_mask[i];
 
-       mes_v11_0_set_gfx_hqd_mask(&mes_set_hw_res_pkt);
+       for (i = 0; i < MAX_GFX_PIPES; i++)
+               mes_set_hw_res_pkt.gfx_hqd_mask[i] =
+                       mes->gfx_hqd_mask[i];
 
        for (i = 0; i < MAX_SDMA_PIPES; i++)
                mes_set_hw_res_pkt.sdma_hqd_mask[i] = mes->sdma_hqd_mask[i];

diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
index 801928555effb75a0b624bd59d20feaf1fa0d706..8892858cfd9ae10016fbb4ce1eb5bb7232825bef 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
@@ -694,17 +694,6 @@ static int mes_v12_0_set_hw_resources_1(struct amdgpu_mes *mes, int pipe)
                        offsetof(union MESAPI_SET_HW_RESOURCES_1, api_status));
 }
 
-static void mes_v12_0_set_gfx_hqd_mask(union MESAPI_SET_HW_RESOURCES *pkt)
-{
-       /*
-        * GFX V12 has only one GFX pipe, but 8 queues in it.
-        * GFX pipe 0 queue 0 is being used by Kernel queue.
-        * Set GFX pipe 0 queue 1-7 for MES scheduling
-        * mask = 1111 1110b
-        */
-       pkt->gfx_hqd_mask[0] = 0xFE;
-}
-
 static int mes_v12_0_set_hw_resources(struct amdgpu_mes *mes, int pipe)
 {
        int i;
@@ -727,7 +716,9 @@ static int mes_v12_0_set_hw_resources(struct amdgpu_mes *mes, int pipe)
                        mes_set_hw_res_pkt.compute_hqd_mask[i] =
                                mes->compute_hqd_mask[i];
 
-               mes_v12_0_set_gfx_hqd_mask(&mes_set_hw_res_pkt);
+               for (i = 0; i < MAX_GFX_PIPES; i++)
+                       mes_set_hw_res_pkt.gfx_hqd_mask[i] =
+                               mes->gfx_hqd_mask[i];
 
                for (i = 0; i < MAX_SDMA_PIPES; i++)
                        mes_set_hw_res_pkt.sdma_hqd_mask[i] =