mt76: set interrupt mask register to 0 before requesting irq
authorFelix Fietkau <nbd@nbd.name>
Fri, 7 Aug 2020 19:55:52 +0000 (21:55 +0200)
committerFelix Fietkau <nbd@nbd.name>
Thu, 24 Sep 2020 16:10:13 +0000 (18:10 +0200)
Avoids spurious interrupts in case the hardware was running already

Signed-off-by: Felix Fietkau <nbd@nbd.name>
drivers/net/wireless/mediatek/mt76/mt7603/pci.c
drivers/net/wireless/mediatek/mt76/mt7603/soc.c
drivers/net/wireless/mediatek/mt76/mt7615/mmio.c
drivers/net/wireless/mediatek/mt76/mt76x0/pci.c
drivers/net/wireless/mediatek/mt76/mt76x2/pci.c
drivers/net/wireless/mediatek/mt76/mt7915/pci.c

index 2f2f337e22014f661fb6d1a56b9a2befec738f70..a5845da3547a93830f59508b5dd247fd804bc0f4 100644 (file)
@@ -44,6 +44,8 @@ mt76pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
                    (mt76_rr(dev, MT_HW_REV) & 0xff);
        dev_info(mdev->dev, "ASIC revision: %04x\n", mdev->rev);
 
+       mt76_wr(dev, MT_INT_MASK_CSR, 0);
+
        ret = devm_request_irq(mdev->dev, pdev->irq, mt7603_irq_handler,
                               IRQF_SHARED, KBUILD_MODNAME, dev);
        if (ret)
index de170765e938dcdaeded5c29bf83a9c64f0ab98a..ba927033bbe8c316d63d2d7a982e056f8300ae91 100644 (file)
@@ -35,6 +35,8 @@ mt76_wmac_probe(struct platform_device *pdev)
                    (mt76_rr(dev, MT_HW_REV) & 0xff);
        dev_info(mdev->dev, "ASIC revision: %04x\n", mdev->rev);
 
+       mt76_wr(dev, MT_INT_MASK_CSR, 0);
+
        ret = devm_request_irq(mdev->dev, irq, mt7603_irq_handler,
                               IRQF_SHARED, KBUILD_MODNAME, dev);
        if (ret)
index 133f93a6ed1b83cc1f55631389e138aab79ec6c9..a0526f06262bcd2a56501f1d63522b63d8dbf8d8 100644 (file)
@@ -227,6 +227,8 @@ int mt7615_mmio_probe(struct device *pdev, void __iomem *mem_base,
        bus_ops->rmw = mt7615_rmw;
        dev->mt76.bus = bus_ops;
 
+       mt76_wr(dev, MT_INT_MASK_CSR, 0);
+
        ret = devm_request_irq(mdev->dev, irq, mt7615_irq_handler,
                               IRQF_SHARED, KBUILD_MODNAME, dev);
        if (ret)
index f7ec3400e368fa70191ceed2476385db3a0b7aed..5e567483b37261a758e51c204e475082a77aa5b3 100644 (file)
@@ -180,6 +180,8 @@ mt76x0e_probe(struct pci_dev *pdev, const struct pci_device_id *id)
        mdev->rev = mt76_rr(dev, MT_ASIC_VERSION);
        dev_info(mdev->dev, "ASIC revision: %08x\n", mdev->rev);
 
+       mt76_wr(dev, MT_INT_MASK_CSR, 0);
+
        ret = devm_request_irq(mdev->dev, pdev->irq, mt76x02_irq_handler,
                               IRQF_SHARED, KBUILD_MODNAME, dev);
        if (ret)
index 6dfb0df8ec8a62b3f5a2e735272ef3e034d3f52a..377cf9c02a6f268f11d3b401f9b1065a076bbc66 100644 (file)
@@ -63,6 +63,8 @@ mt76x2e_probe(struct pci_dev *pdev, const struct pci_device_id *id)
        mdev->rev = mt76_rr(dev, MT_ASIC_VERSION);
        dev_info(mdev->dev, "ASIC revision: %08x\n", mdev->rev);
 
+       mt76_wr(dev, MT_INT_MASK_CSR, 0);
+
        ret = devm_request_irq(mdev->dev, pdev->irq, mt76x02_irq_handler,
                               IRQF_SHARED, KBUILD_MODNAME, dev);
        if (ret)
index 0ec4e184b889789f945ddb996a2dec02b96552bf..1908a0d99c90e9f90d704f8d5ea0f7711b6aea6d 100644 (file)
@@ -149,6 +149,8 @@ static int mt7915_pci_probe(struct pci_dev *pdev,
                    (mt7915_l1_rr(dev, MT_HW_REV) & 0xff);
        dev_dbg(mdev->dev, "ASIC revision: %04x\n", mdev->rev);
 
+       mt76_wr(dev, MT_INT_MASK_CSR, 0);
+
        /* master switch of PCIe tnterrupt enable */
        mt7915_l1_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0xff);