PCI: qcom-ep: Mark BAR0/BAR2 as 64bit BARs and BAR1/BAR3 as RESERVED

On all Qcom endpoint SoCs, BAR0/BAR2 are 64bit BARs by default and
software cannot change the type.

So, mark the those BARs as 64bit BARs and also mark the successive
BAR1/BAR3 as RESERVED BARs so that the EPF drivers cannot use them.

Cc: stable+noautosel@kernel.org # depends on patch introducing only_64bit flag
Fixes: f55fee56a631 ("PCI: qcom-ep: Add Qualcomm PCIe Endpoint controller driver")
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20241231130224.38206-3-manivannan.sadhasivam@linaro.org
[kwilczynski: commit log]
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>

diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c
index c08f64d7a825fa5da22976c8020f96ee5faa5462..01d3862d7003ff35d54ca67c7dc3dc4ad62dc1a4 100644 (file)
--- a/drivers/pci/controller/dwc/pcie-qcom-ep.c
+++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c
@@ -825,6 +825,10 @@ static const struct pci_epc_features qcom_pcie_epc_features = {
        .msi_capable = true,
        .msix_capable = false,
        .align = SZ_4K,
+       .bar[BAR_0] = { .only_64bit = true, },
+       .bar[BAR_1] = { .type = BAR_RESERVED, },
+       .bar[BAR_2] = { .only_64bit = true, },
+       .bar[BAR_3] = { .type = BAR_RESERVED, },
 };
 
 static const struct pci_epc_features *