net: rswitch: Set GWMDNC register
authorYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Fri, 8 Dec 2023 04:10:27 +0000 (13:10 +0900)
committerDavid S. Miller <davem@davemloft.net>
Sun, 10 Dec 2023 19:31:41 +0000 (19:31 +0000)
To support jumbo frames, set GWMDNC register with acceptable maximum
values for TX and RX.

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/ethernet/renesas/rswitch.c
drivers/net/ethernet/renesas/rswitch.h

index eda5ea56674cb014631a259d90e9d35c26c5e063..6bd76a88bd40ef539009c35fa672a764c25a4a0b 100644 (file)
@@ -668,6 +668,8 @@ static int rswitch_gwca_hw_init(struct rswitch_private *priv)
        iowrite32(upper_32_bits(priv->gwca.linkfix_table_dma), priv->addr + GWDCBAC0);
        iowrite32(lower_32_bits(priv->gwca.ts_queue.ring_dma), priv->addr + GWTDCAC10);
        iowrite32(upper_32_bits(priv->gwca.ts_queue.ring_dma), priv->addr + GWTDCAC00);
+       iowrite32(GWMDNC_TSDMN(1) | GWMDNC_TXDMN(0x1e) | GWMDNC_RXDMN(0x1f),
+                 priv->addr + GWMDNC);
        iowrite32(GWCA_TS_IRQ_BIT, priv->addr + GWTSDCC0);
 
        iowrite32(GWTPC_PPPL(GWCA_IPV_NUM), priv->addr + GWTPC0);
index 2ac9a86b6238cec9aaad4e07284b424d23ca3d46..17e617ec4187b2c48f243c2942ef3864a0f3b278 100644 (file)
@@ -773,6 +773,10 @@ enum rswitch_gwca_mode {
 #define GWARIRM_ARIOG          BIT(0)
 #define GWARIRM_ARR            BIT(1)
 
+#define GWMDNC_TSDMN(num)      (((num) << 16) & GENMASK(17, 16))
+#define GWMDNC_TXDMN(num)      (((num) << 8) & GENMASK(12, 8))
+#define GWMDNC_RXDMN(num)      ((num) & GENMASK(4, 0))
+
 #define GWDCC_BALR             BIT(24)
 #define GWDCC_DCP_MASK         GENMASK(18, 16)
 #define GWDCC_DCP(prio)                FIELD_PREP(GWDCC_DCP_MASK, (prio))