net: dsa: mt7530: refactor MT7530_MFC and MT7531_CFC, add MT7531_QRY_FFP

The MT7530_MFC register is on MT7530, MT7531, and the switch on the MT7988
SoC. Rename it to MT753X_MFC. Bit 7 to 0 differs between MT7530 and
MT7531/MT7988. Add MT7530 prefix to these definitions, and define the
IGMP/MLD Query Frame Flooding Ports mask for MT7531.

Rename the cases of MIRROR_MASK to MIRROR_PORT_MASK.

Move mt753x_mirror_port_get() and mt753x_port_mirror_set() to mt7530.h as
macros.

Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c
index 7f864f895ba0be64068c230fbd40eed0473e7929..39c47499036b14ffb8ac12181e4d4de29c60a420 100644 (file)
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
@@ -1147,7 +1147,7 @@ mt753x_cpu_port_enable(struct dsa_switch *ds, int port)
                     PORT_SPEC_TAG);
 
        /* Enable flooding on the CPU port */
-       mt7530_set(priv, MT7530_MFC, BC_FFP(BIT(port)) | UNM_FFP(BIT(port)) |
+       mt7530_set(priv, MT753X_MFC, BC_FFP(BIT(port)) | UNM_FFP(BIT(port)) |
                   UNU_FFP(BIT(port)));
 
        /* Add the CPU port to the CPU port bitmap for MT7531 and the switch on
@@ -1311,15 +1311,15 @@ mt7530_port_bridge_flags(struct dsa_switch *ds, int port,
                           flags.val & BR_LEARNING ? 0 : SA_DIS);
 
        if (flags.mask & BR_FLOOD)
-               mt7530_rmw(priv, MT7530_MFC, UNU_FFP(BIT(port)),
+               mt7530_rmw(priv, MT753X_MFC, UNU_FFP(BIT(port)),
                           flags.val & BR_FLOOD ? UNU_FFP(BIT(port)) : 0);
 
        if (flags.mask & BR_MCAST_FLOOD)
-               mt7530_rmw(priv, MT7530_MFC, UNM_FFP(BIT(port)),
+               mt7530_rmw(priv, MT753X_MFC, UNM_FFP(BIT(port)),
                           flags.val & BR_MCAST_FLOOD ? UNM_FFP(BIT(port)) : 0);
 
        if (flags.mask & BR_BCAST_FLOOD)
-               mt7530_rmw(priv, MT7530_MFC, BC_FFP(BIT(port)),
+               mt7530_rmw(priv, MT753X_MFC, BC_FFP(BIT(port)),
                           flags.val & BR_BCAST_FLOOD ? BC_FFP(BIT(port)) : 0);
 
        return 0;
@@ -1855,20 +1855,6 @@ mt7530_port_vlan_del(struct dsa_switch *ds, int port,
        return 0;
 }
 
-static int mt753x_mirror_port_get(unsigned int id, u32 val)
-{
-       return (id == ID_MT7531 || id == ID_MT7988) ?
-                      MT7531_MIRROR_PORT_GET(val) :
-                      MIRROR_PORT(val);
-}
-
-static int mt753x_mirror_port_set(unsigned int id, u32 val)
-{
-       return (id == ID_MT7531 || id == ID_MT7988) ?
-                      MT7531_MIRROR_PORT_SET(val) :
-                      MIRROR_PORT(val);
-}
-
 static int mt753x_port_mirror_add(struct dsa_switch *ds, int port,
                                  struct dsa_mall_mirror_tc_entry *mirror,
                                  bool ingress, struct netlink_ext_ack *extack)
@@ -1884,14 +1870,14 @@ static int mt753x_port_mirror_add(struct dsa_switch *ds, int port,
        val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id));
 
        /* MT7530 only supports one monitor port */
-       monitor_port = mt753x_mirror_port_get(priv->id, val);
+       monitor_port = MT753X_MIRROR_PORT_GET(priv->id, val);
        if (val & MT753X_MIRROR_EN(priv->id) &&
            monitor_port != mirror->to_local_port)
                return -EEXIST;
 
        val |= MT753X_MIRROR_EN(priv->id);
-       val &= ~MT753X_MIRROR_MASK(priv->id);
-       val |= mt753x_mirror_port_set(priv->id, mirror->to_local_port);
+       val &= ~MT753X_MIRROR_PORT_MASK(priv->id);
+       val |= MT753X_MIRROR_PORT_SET(priv->id, mirror->to_local_port);
        mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val);
 
        val = mt7530_read(priv, MT7530_PCR_P(port));
@@ -2533,7 +2519,7 @@ mt7531_setup_common(struct dsa_switch *ds)
        mt7530_mib_reset(ds);
 
        /* Disable flooding on all ports */
-       mt7530_clear(priv, MT7530_MFC, BC_FFP_MASK | UNM_FFP_MASK |
+       mt7530_clear(priv, MT753X_MFC, BC_FFP_MASK | UNM_FFP_MASK |
                     UNU_FFP_MASK);
 
        for (i = 0; i < MT7530_NUM_PORTS; i++) {
@@ -3089,10 +3075,12 @@ mt753x_conduit_state_change(struct dsa_switch *ds,
        else
                priv->active_cpu_ports &= ~mask;
 
-       if (priv->active_cpu_ports)
-               val = CPU_EN | CPU_PORT(__ffs(priv->active_cpu_ports));
+       if (priv->active_cpu_ports) {
+               val = MT7530_CPU_EN |
+                     MT7530_CPU_PORT(__ffs(priv->active_cpu_ports));
+       }
 
-       mt7530_rmw(priv, MT7530_MFC, CPU_EN | CPU_PORT_MASK, val);
+       mt7530_rmw(priv, MT753X_MFC, MT7530_CPU_EN | MT7530_CPU_PORT_MASK, val);
 }
 
 static int mt7988_setup(struct dsa_switch *ds)

diff --git a/drivers/net/dsa/mt7530.h b/drivers/net/dsa/mt7530.h
index 0d5167f5ba6bcdc3d6a2bb1b076a4f8a394e06e9..c6ef20b7bbdd9a9c5e0a7098cc34754b643bec88 100644 (file)
--- a/drivers/net/dsa/mt7530.h
+++ b/drivers/net/dsa/mt7530.h
@@ -36,36 +36,55 @@ enum mt753x_id {
 #define MT753X_AGC                     0xc
 #define  LOCAL_EN                      BIT(7)
 
-/* Registers to mac forward control for unknown frames */
-#define MT7530_MFC                     0x10
-#define  BC_FFP(x)                     (((x) & 0xff) << 24)
-#define  BC_FFP_MASK                   BC_FFP(~0)
-#define  UNM_FFP(x)                    (((x) & 0xff) << 16)
-#define  UNM_FFP_MASK                  UNM_FFP(~0)
-#define  UNU_FFP(x)                    (((x) & 0xff) << 8)
-#define  UNU_FFP_MASK                  UNU_FFP(~0)
-#define  CPU_EN                                BIT(7)
-#define  CPU_PORT_MASK                 GENMASK(6, 4)
-#define  CPU_PORT(x)                   FIELD_PREP(CPU_PORT_MASK, x)
-#define  MIRROR_EN                     BIT(3)
-#define  MIRROR_PORT(x)                        ((x) & 0x7)
-#define  MIRROR_MASK                   0x7
-
-/* Registers for CPU forward control */
+/* Register for MAC forward control */
+#define MT753X_MFC                     0x10
+#define  BC_FFP_MASK                   GENMASK(31, 24)
+#define  BC_FFP(x)                     FIELD_PREP(BC_FFP_MASK, x)
+#define  UNM_FFP_MASK                  GENMASK(23, 16)
+#define  UNM_FFP(x)                    FIELD_PREP(UNM_FFP_MASK, x)
+#define  UNU_FFP_MASK                  GENMASK(15, 8)
+#define  UNU_FFP(x)                    FIELD_PREP(UNU_FFP_MASK, x)
+#define  MT7530_CPU_EN                 BIT(7)
+#define  MT7530_CPU_PORT_MASK          GENMASK(6, 4)
+#define  MT7530_CPU_PORT(x)            FIELD_PREP(MT7530_CPU_PORT_MASK, x)
+#define  MT7530_MIRROR_EN              BIT(3)
+#define  MT7530_MIRROR_PORT_MASK       GENMASK(2, 0)
+#define  MT7530_MIRROR_PORT_GET(x)     FIELD_GET(MT7530_MIRROR_PORT_MASK, x)
+#define  MT7530_MIRROR_PORT_SET(x)     FIELD_PREP(MT7530_MIRROR_PORT_MASK, x)
+#define  MT7531_QRY_FFP_MASK           GENMASK(7, 0)
+#define  MT7531_QRY_FFP(x)             FIELD_PREP(MT7531_QRY_FFP_MASK, x)
+
+/* Register for CPU forward control */
 #define MT7531_CFC                     0x4
 #define  MT7531_MIRROR_EN              BIT(19)
-#define  MT7531_MIRROR_MASK            (MIRROR_MASK << 16)
-#define  MT7531_MIRROR_PORT_GET(x)     (((x) >> 16) & MIRROR_MASK)
-#define  MT7531_MIRROR_PORT_SET(x)     (((x) & MIRROR_MASK) << 16)
+#define  MT7531_MIRROR_PORT_MASK       GENMASK(18, 16)
+#define  MT7531_MIRROR_PORT_GET(x)     FIELD_GET(MT7531_MIRROR_PORT_MASK, x)
+#define  MT7531_MIRROR_PORT_SET(x)     FIELD_PREP(MT7531_MIRROR_PORT_MASK, x)
 #define  MT7531_CPU_PMAP_MASK          GENMASK(7, 0)
 #define  MT7531_CPU_PMAP(x)            FIELD_PREP(MT7531_CPU_PMAP_MASK, x)
 
-#define MT753X_MIRROR_REG(id)          ((((id) == ID_MT7531) || ((id) == ID_MT7988)) ? \
-                                        MT7531_CFC : MT7530_MFC)
-#define MT753X_MIRROR_EN(id)           ((((id) == ID_MT7531) || ((id) == ID_MT7988)) ? \
-                                        MT7531_MIRROR_EN : MIRROR_EN)
-#define MT753X_MIRROR_MASK(id)         ((((id) == ID_MT7531) || ((id) == ID_MT7988)) ? \
-                                        MT7531_MIRROR_MASK : MIRROR_MASK)
+#define MT753X_MIRROR_REG(id)          ((id == ID_MT7531 || \
+                                         id == ID_MT7988) ? \
+                                        MT7531_CFC : MT753X_MFC)
+
+#define MT753X_MIRROR_EN(id)           ((id == ID_MT7531 || \
+                                         id == ID_MT7988) ? \
+                                        MT7531_MIRROR_EN : MT7530_MIRROR_EN)
+
+#define MT753X_MIRROR_PORT_MASK(id)    ((id == ID_MT7531 || \
+                                         id == ID_MT7988) ? \
+                                        MT7531_MIRROR_PORT_MASK : \
+                                        MT7530_MIRROR_PORT_MASK)
+
+#define MT753X_MIRROR_PORT_GET(id, val)        ((id == ID_MT7531 || \
+                                         id == ID_MT7988) ? \
+                                        MT7531_MIRROR_PORT_GET(val) : \
+                                        MT7530_MIRROR_PORT_GET(val))
+
+#define MT753X_MIRROR_PORT_SET(id, val)        ((id == ID_MT7531 || \
+                                         id == ID_MT7988) ? \
+                                        MT7531_MIRROR_PORT_SET(val) : \
+                                        MT7530_MIRROR_PORT_SET(val))
 
 /* Register for BPDU and PAE frame control */
 #define MT753X_BPC                     0x24