drm/i915: move display_irqs_enabled to display substruct
authorJani Nikula <jani.nikula@intel.com>
Mon, 8 Apr 2024 18:08:40 +0000 (21:08 +0300)
committerJani Nikula <jani.nikula@intel.com>
Tue, 9 Apr 2024 08:31:15 +0000 (11:31 +0300)
The info is related to display, and should be placed under
i915->display.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Acked-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/f6ac8e4c6ec8621bacf3db58a2bf156bd636f1d1.1712599670.git.jani.nikula@intel.com
drivers/gpu/drm/i915/display/intel_display_core.h
drivers/gpu/drm/i915/display/intel_display_irq.c
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
drivers/gpu/drm/i915/i915_drv.h
drivers/gpu/drm/i915/i915_irq.c
drivers/gpu/drm/xe/xe_device_types.h

index 52f7d6e0324f4e94e052cc2ade63723ab0a85e73..68aee44b48224b8a74b273c4fba2d77e9b9c1b72 100644 (file)
@@ -448,6 +448,8 @@ struct intel_display {
        } ips;
 
        struct {
+               bool display_irqs_enabled;
+
                /* For i915gm/i945gm vblank irq workaround */
                u8 vblank_enabled;
        } irq;
index 6219b1a622102e9c62b309df3299f95adbc7ae4e..e9fcdac90efdc32b84583da2dea32135fbb82a7d 100644 (file)
@@ -412,7 +412,7 @@ void i9xx_pipestat_irq_ack(struct drm_i915_private *dev_priv,
 
        spin_lock(&dev_priv->irq_lock);
 
-       if (!dev_priv->display_irqs_enabled) {
+       if (!dev_priv->display.irq.display_irqs_enabled) {
                spin_unlock(&dev_priv->irq_lock);
                return;
        }
@@ -1558,10 +1558,10 @@ void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
 {
        lockdep_assert_held(&dev_priv->irq_lock);
 
-       if (dev_priv->display_irqs_enabled)
+       if (dev_priv->display.irq.display_irqs_enabled)
                return;
 
-       dev_priv->display_irqs_enabled = true;
+       dev_priv->display.irq.display_irqs_enabled = true;
 
        if (intel_irqs_enabled(dev_priv)) {
                vlv_display_irq_reset(dev_priv);
@@ -1573,10 +1573,10 @@ void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
 {
        lockdep_assert_held(&dev_priv->irq_lock);
 
-       if (!dev_priv->display_irqs_enabled)
+       if (!dev_priv->display.irq.display_irqs_enabled)
                return;
 
-       dev_priv->display_irqs_enabled = false;
+       dev_priv->display.irq.display_irqs_enabled = false;
 
        if (intel_irqs_enabled(dev_priv))
                vlv_display_irq_reset(dev_priv);
@@ -1770,9 +1770,9 @@ void intel_display_irq_init(struct drm_i915_private *i915)
         * domain. We defer setting up the display irqs in this case to the
         * runtime pm.
         */
-       i915->display_irqs_enabled = true;
+       i915->display.irq.display_irqs_enabled = true;
        if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
-               i915->display_irqs_enabled = false;
+               i915->display.irq.display_irqs_enabled = false;
 
        intel_hotplug_irq_init(i915);
 }
index 76076509f7717f86657f9b975fe1f1c0b7bf875b..d270bb7b9462f3064005cd1a8d2e759574df3c8a 100644 (file)
@@ -1444,7 +1444,7 @@ void intel_hpd_enable_detection(struct intel_encoder *encoder)
 
 void intel_hpd_irq_setup(struct drm_i915_private *i915)
 {
-       if (i915->display_irqs_enabled && i915->display.funcs.hotplug)
+       if (i915->display.irq.display_irqs_enabled && i915->display.funcs.hotplug)
                i915->display.funcs.hotplug->hpd_irq_setup(i915);
 }
 
index a835537315383ff09427e0bc629c1f9f775a6856..b3daca57f32c510623c443866309268abf579fb3 100644 (file)
@@ -235,8 +235,6 @@ struct drm_i915_private {
        /* protects the irq masks */
        spinlock_t irq_lock;
 
-       bool display_irqs_enabled;
-
        /* Sideband mailbox protection */
        struct mutex sb_lock;
        struct pm_qos_request sb_qos;
index 8130f043693b17c7f15a902e9eb080c7de760f00..678d632ed043ca96bdebd9bed6ba9770a8db4189 100644 (file)
@@ -702,7 +702,7 @@ static void valleyview_irq_reset(struct drm_i915_private *dev_priv)
        gen5_gt_irq_reset(to_gt(dev_priv));
 
        spin_lock_irq(&dev_priv->irq_lock);
-       if (dev_priv->display_irqs_enabled)
+       if (dev_priv->display.irq.display_irqs_enabled)
                vlv_display_irq_reset(dev_priv);
        spin_unlock_irq(&dev_priv->irq_lock);
 }
@@ -767,7 +767,7 @@ static void cherryview_irq_reset(struct drm_i915_private *dev_priv)
        GEN3_IRQ_RESET(uncore, GEN8_PCU_);
 
        spin_lock_irq(&dev_priv->irq_lock);
-       if (dev_priv->display_irqs_enabled)
+       if (dev_priv->display.irq.display_irqs_enabled)
                vlv_display_irq_reset(dev_priv);
        spin_unlock_irq(&dev_priv->irq_lock);
 }
@@ -784,7 +784,7 @@ static void valleyview_irq_postinstall(struct drm_i915_private *dev_priv)
        gen5_gt_irq_postinstall(to_gt(dev_priv));
 
        spin_lock_irq(&dev_priv->irq_lock);
-       if (dev_priv->display_irqs_enabled)
+       if (dev_priv->display.irq.display_irqs_enabled)
                vlv_display_irq_postinstall(dev_priv);
        spin_unlock_irq(&dev_priv->irq_lock);
 
@@ -838,7 +838,7 @@ static void cherryview_irq_postinstall(struct drm_i915_private *dev_priv)
        gen8_gt_irq_postinstall(to_gt(dev_priv));
 
        spin_lock_irq(&dev_priv->irq_lock);
-       if (dev_priv->display_irqs_enabled)
+       if (dev_priv->display.irq.display_irqs_enabled)
                vlv_display_irq_postinstall(dev_priv);
        spin_unlock_irq(&dev_priv->irq_lock);
 
index e19b022a095f14d2d56adbff7cbcce8512998d17..a8844a147cdfb4d0de746bad77365950f0638133 100644 (file)
@@ -504,7 +504,6 @@ struct xe_device {
        };
        u32 pipestat_irq_mask[I915_MAX_PIPES];
 
-       bool display_irqs_enabled;
        u32 enabled_irq_mask;
 
        struct intel_uncore {