drm/i915/xe2lpd: display capability register definitions

Register definitions to track the reported scalable display
feature configurations

Bspec: 71161
Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20231001113155.80659-2-vinod.govindapillai@intel.com
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1a9ca1e530bc47cecd409c9fc75c14c2067afc9a..135e8d8dbdf06a2333cddb98719bace133b0dfe1 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4680,6 +4680,13 @@
 #define   TGL_DFSM_PIPE_D_DISABLE      (1 << 22)
 #define   GLK_DFSM_DISPLAY_DSC_DISABLE (1 << 7)
 
+#define XE2LPD_DE_CAP                  _MMIO(0x41100)
+#define   XE2LPD_DE_CAP_3DLUT_MASK     REG_GENMASK(31, 30)
+#define   XE2LPD_DE_CAP_DSC_MASK       REG_GENMASK(29, 28)
+#define   XE2LPD_DE_CAP_DSC_REMOVED    1
+#define   XE2LPD_DE_CAP_SCALER_MASK    REG_GENMASK(27, 26)
+#define   XE2LPD_DE_CAP_SCALER_SINGLE  1
+
 #define SKL_DSSM                               _MMIO(0x51004)
 #define ICL_DSSM_CDCLK_PLL_REFCLK_MASK         (7 << 29)
 #define ICL_DSSM_CDCLK_PLL_REFCLK_24MHz                (0 << 29)