};
static void sh_msiof_spi_set_clk_regs(struct sh_msiof_spi_priv *p,
- unsigned long parent_rate, u32 spi_hz)
+ struct spi_transfer *t)
{
+ unsigned long parent_rate = clk_get_rate(p->clk);
+ unsigned int div_pow = p->min_div_pow;
+ u32 spi_hz = t->speed_hz;
unsigned long div;
u32 brps, scr;
- unsigned int div_pow = p->min_div_pow;
if (!spi_hz || !parent_rate) {
WARN(1, "Invalid clock rate parameters %lu and %u\n",
brps = 32;
}
+ t->effective_speed_hz = parent_rate / (brps << div_pow);
+
scr = sh_msiof_spi_div_array[div_pow] | SISCR_BRPS(brps);
sh_msiof_write(p, SITSCR, scr);
if (!(p->ctlr->flags & SPI_CONTROLLER_MUST_TX))
/* setup clocks (clock already enabled in chipselect()) */
if (!spi_controller_is_slave(p->ctlr))
- sh_msiof_spi_set_clk_regs(p, clk_get_rate(p->clk), t->speed_hz);
+ sh_msiof_spi_set_clk_regs(p, t);
while (ctlr->dma_tx && len > 15) {
/*