drm/amd/display: CNVC pseudocode review follow up

Signed-off-by: Yue Hin Lau <Yuehin.Lau@amd.com>
Reviewed-by: Eric Bernstein <Eric.Bernstein@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
index 375fb457e22353c0714464aa1142dc867879d190..e39568b4460c86850cfa140d4a0c7bea8a900355 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
@@ -226,7 +226,7 @@ bool dc_stream_set_cursor_attributes(
                if (pipe_ctx->plane_res.dpp != NULL &&
                                pipe_ctx->plane_res.dpp->funcs->set_cursor_attributes != NULL)
                        pipe_ctx->plane_res.dpp->funcs->set_cursor_attributes(
-                               pipe_ctx->plane_res.dpp, attributes);
+                               pipe_ctx->plane_res.dpp, attributes->color_format);
        }
 
        stream->cursor_attributes = *attributes;

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
index 8df3945370cf1d8fe052aee667862658df4db6f4..5a95fa03bc17524bb92e6bf53a542afbe2b9f799 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
@@ -386,10 +386,9 @@ void dpp1_cnv_setup (
 
 void dpp1_set_cursor_attributes(
                struct dpp *dpp_base,
-               const struct dc_cursor_attributes *attr)
+               enum dc_cursor_color_format color_format)
 {
        struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
-       enum dc_cursor_color_format color_format = attr->color_format;
 
        REG_UPDATE_2(CURSOR0_CONTROL,
                        CUR0_MODE, color_format,

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
index ad71fb50f8a51793c6673c0f3e3a4d4d3a421570..41f0c84bfa097cf11b22804d1bacf0db59f4727d 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
@@ -1005,258 +1005,256 @@
        type CM_BYPASS; \
        type FORMAT_CONTROL__ALPHA_EN; \
        type CUR0_COLOR0; \
-       type CUR0_COLOR1
-
-
+       type CUR0_COLOR1;
 
 struct dcn_dpp_shift {
-       TF_REG_FIELD_LIST(uint8_t);
+       TF_REG_FIELD_LIST(uint8_t)
 };
 
 struct dcn_dpp_mask {
-       TF_REG_FIELD_LIST(uint32_t);
+       TF_REG_FIELD_LIST(uint32_t)
 };
 
-
-
+#define DPP_COMMON_REG_VARIABLE_LIST \
+       uint32_t DSCL_EXT_OVERSCAN_LEFT_RIGHT; \
+       uint32_t DSCL_EXT_OVERSCAN_TOP_BOTTOM; \
+       uint32_t OTG_H_BLANK; \
+       uint32_t OTG_V_BLANK; \
+       uint32_t SCL_MODE; \
+       uint32_t LB_DATA_FORMAT; \
+       uint32_t LB_MEMORY_CTRL; \
+       uint32_t DSCL_AUTOCAL; \
+       uint32_t SCL_BLACK_OFFSET; \
+       uint32_t SCL_TAP_CONTROL; \
+       uint32_t SCL_COEF_RAM_TAP_SELECT; \
+       uint32_t SCL_COEF_RAM_TAP_DATA; \
+       uint32_t DSCL_2TAP_CONTROL; \
+       uint32_t MPC_SIZE; \
+       uint32_t SCL_HORZ_FILTER_SCALE_RATIO; \
+       uint32_t SCL_VERT_FILTER_SCALE_RATIO; \
+       uint32_t SCL_HORZ_FILTER_SCALE_RATIO_C; \
+       uint32_t SCL_VERT_FILTER_SCALE_RATIO_C; \
+       uint32_t SCL_HORZ_FILTER_INIT; \
+       uint32_t SCL_HORZ_FILTER_INIT_C; \
+       uint32_t SCL_VERT_FILTER_INIT; \
+       uint32_t SCL_VERT_FILTER_INIT_BOT; \
+       uint32_t SCL_VERT_FILTER_INIT_C; \
+       uint32_t SCL_VERT_FILTER_INIT_BOT_C; \
+       uint32_t RECOUT_START; \
+       uint32_t RECOUT_SIZE; \
+       uint32_t CM_GAMUT_REMAP_CONTROL; \
+       uint32_t CM_GAMUT_REMAP_C11_C12; \
+       uint32_t CM_GAMUT_REMAP_C33_C34; \
+       uint32_t CM_COMA_C11_C12; \
+       uint32_t CM_COMA_C33_C34; \
+       uint32_t CM_COMB_C11_C12; \
+       uint32_t CM_COMB_C33_C34; \
+       uint32_t CM_OCSC_CONTROL; \
+       uint32_t CM_OCSC_C11_C12; \
+       uint32_t CM_OCSC_C33_C34; \
+       uint32_t CM_MEM_PWR_CTRL; \
+       uint32_t CM_RGAM_LUT_DATA; \
+       uint32_t CM_RGAM_LUT_WRITE_EN_MASK; \
+       uint32_t CM_RGAM_LUT_INDEX; \
+       uint32_t CM_RGAM_RAMB_START_CNTL_B; \
+       uint32_t CM_RGAM_RAMB_START_CNTL_G; \
+       uint32_t CM_RGAM_RAMB_START_CNTL_R; \
+       uint32_t CM_RGAM_RAMB_SLOPE_CNTL_B; \
+       uint32_t CM_RGAM_RAMB_SLOPE_CNTL_G; \
+       uint32_t CM_RGAM_RAMB_SLOPE_CNTL_R; \
+       uint32_t CM_RGAM_RAMB_END_CNTL1_B; \
+       uint32_t CM_RGAM_RAMB_END_CNTL2_B; \
+       uint32_t CM_RGAM_RAMB_END_CNTL1_G; \
+       uint32_t CM_RGAM_RAMB_END_CNTL2_G; \
+       uint32_t CM_RGAM_RAMB_END_CNTL1_R; \
+       uint32_t CM_RGAM_RAMB_END_CNTL2_R; \
+       uint32_t CM_RGAM_RAMB_REGION_0_1; \
+       uint32_t CM_RGAM_RAMB_REGION_32_33; \
+       uint32_t CM_RGAM_RAMA_START_CNTL_B; \
+       uint32_t CM_RGAM_RAMA_START_CNTL_G; \
+       uint32_t CM_RGAM_RAMA_START_CNTL_R; \
+       uint32_t CM_RGAM_RAMA_SLOPE_CNTL_B; \
+       uint32_t CM_RGAM_RAMA_SLOPE_CNTL_G; \
+       uint32_t CM_RGAM_RAMA_SLOPE_CNTL_R; \
+       uint32_t CM_RGAM_RAMA_END_CNTL1_B; \
+       uint32_t CM_RGAM_RAMA_END_CNTL2_B; \
+       uint32_t CM_RGAM_RAMA_END_CNTL1_G; \
+       uint32_t CM_RGAM_RAMA_END_CNTL2_G; \
+       uint32_t CM_RGAM_RAMA_END_CNTL1_R; \
+       uint32_t CM_RGAM_RAMA_END_CNTL2_R; \
+       uint32_t CM_RGAM_RAMA_REGION_0_1; \
+       uint32_t CM_RGAM_RAMA_REGION_32_33; \
+       uint32_t CM_RGAM_CONTROL; \
+       uint32_t CM_CMOUT_CONTROL; \
+       uint32_t CM_BLNDGAM_LUT_WRITE_EN_MASK; \
+       uint32_t CM_BLNDGAM_CONTROL; \
+       uint32_t CM_BLNDGAM_RAMB_START_CNTL_B; \
+       uint32_t CM_BLNDGAM_RAMB_START_CNTL_G; \
+       uint32_t CM_BLNDGAM_RAMB_START_CNTL_R; \
+       uint32_t CM_BLNDGAM_RAMB_SLOPE_CNTL_B; \
+       uint32_t CM_BLNDGAM_RAMB_SLOPE_CNTL_G; \
+       uint32_t CM_BLNDGAM_RAMB_SLOPE_CNTL_R; \
+       uint32_t CM_BLNDGAM_RAMB_END_CNTL1_B; \
+       uint32_t CM_BLNDGAM_RAMB_END_CNTL2_B; \
+       uint32_t CM_BLNDGAM_RAMB_END_CNTL1_G; \
+       uint32_t CM_BLNDGAM_RAMB_END_CNTL2_G; \
+       uint32_t CM_BLNDGAM_RAMB_END_CNTL1_R; \
+       uint32_t CM_BLNDGAM_RAMB_END_CNTL2_R; \
+       uint32_t CM_BLNDGAM_RAMB_REGION_0_1; \
+       uint32_t CM_BLNDGAM_RAMB_REGION_2_3; \
+       uint32_t CM_BLNDGAM_RAMB_REGION_4_5; \
+       uint32_t CM_BLNDGAM_RAMB_REGION_6_7; \
+       uint32_t CM_BLNDGAM_RAMB_REGION_8_9; \
+       uint32_t CM_BLNDGAM_RAMB_REGION_10_11; \
+       uint32_t CM_BLNDGAM_RAMB_REGION_12_13; \
+       uint32_t CM_BLNDGAM_RAMB_REGION_14_15; \
+       uint32_t CM_BLNDGAM_RAMB_REGION_16_17; \
+       uint32_t CM_BLNDGAM_RAMB_REGION_18_19; \
+       uint32_t CM_BLNDGAM_RAMB_REGION_20_21; \
+       uint32_t CM_BLNDGAM_RAMB_REGION_22_23; \
+       uint32_t CM_BLNDGAM_RAMB_REGION_24_25; \
+       uint32_t CM_BLNDGAM_RAMB_REGION_26_27; \
+       uint32_t CM_BLNDGAM_RAMB_REGION_28_29; \
+       uint32_t CM_BLNDGAM_RAMB_REGION_30_31; \
+       uint32_t CM_BLNDGAM_RAMB_REGION_32_33; \
+       uint32_t CM_BLNDGAM_RAMA_START_CNTL_B; \
+       uint32_t CM_BLNDGAM_RAMA_START_CNTL_G; \
+       uint32_t CM_BLNDGAM_RAMA_START_CNTL_R; \
+       uint32_t CM_BLNDGAM_RAMA_SLOPE_CNTL_B; \
+       uint32_t CM_BLNDGAM_RAMA_SLOPE_CNTL_G; \
+       uint32_t CM_BLNDGAM_RAMA_SLOPE_CNTL_R; \
+       uint32_t CM_BLNDGAM_RAMA_END_CNTL1_B; \
+       uint32_t CM_BLNDGAM_RAMA_END_CNTL2_B; \
+       uint32_t CM_BLNDGAM_RAMA_END_CNTL1_G; \
+       uint32_t CM_BLNDGAM_RAMA_END_CNTL2_G; \
+       uint32_t CM_BLNDGAM_RAMA_END_CNTL1_R; \
+       uint32_t CM_BLNDGAM_RAMA_END_CNTL2_R; \
+       uint32_t CM_BLNDGAM_RAMA_REGION_0_1; \
+       uint32_t CM_BLNDGAM_RAMA_REGION_2_3; \
+       uint32_t CM_BLNDGAM_RAMA_REGION_4_5; \
+       uint32_t CM_BLNDGAM_RAMA_REGION_6_7; \
+       uint32_t CM_BLNDGAM_RAMA_REGION_8_9; \
+       uint32_t CM_BLNDGAM_RAMA_REGION_10_11; \
+       uint32_t CM_BLNDGAM_RAMA_REGION_12_13; \
+       uint32_t CM_BLNDGAM_RAMA_REGION_14_15; \
+       uint32_t CM_BLNDGAM_RAMA_REGION_16_17; \
+       uint32_t CM_BLNDGAM_RAMA_REGION_18_19; \
+       uint32_t CM_BLNDGAM_RAMA_REGION_20_21; \
+       uint32_t CM_BLNDGAM_RAMA_REGION_22_23; \
+       uint32_t CM_BLNDGAM_RAMA_REGION_24_25; \
+       uint32_t CM_BLNDGAM_RAMA_REGION_26_27; \
+       uint32_t CM_BLNDGAM_RAMA_REGION_28_29; \
+       uint32_t CM_BLNDGAM_RAMA_REGION_30_31; \
+       uint32_t CM_BLNDGAM_RAMA_REGION_32_33; \
+       uint32_t CM_BLNDGAM_LUT_INDEX; \
+       uint32_t CM_BLNDGAM_LUT_DATA; \
+       uint32_t CM_3DLUT_MODE; \
+       uint32_t CM_3DLUT_INDEX; \
+       uint32_t CM_3DLUT_DATA; \
+       uint32_t CM_3DLUT_DATA_30BIT; \
+       uint32_t CM_3DLUT_READ_WRITE_CONTROL; \
+       uint32_t CM_SHAPER_LUT_WRITE_EN_MASK; \
+       uint32_t CM_SHAPER_CONTROL; \
+       uint32_t CM_SHAPER_RAMB_START_CNTL_B; \
+       uint32_t CM_SHAPER_RAMB_START_CNTL_G; \
+       uint32_t CM_SHAPER_RAMB_START_CNTL_R; \
+       uint32_t CM_SHAPER_RAMB_END_CNTL_B; \
+       uint32_t CM_SHAPER_RAMB_END_CNTL_G; \
+       uint32_t CM_SHAPER_RAMB_END_CNTL_R; \
+       uint32_t CM_SHAPER_RAMB_REGION_0_1; \
+       uint32_t CM_SHAPER_RAMB_REGION_2_3; \
+       uint32_t CM_SHAPER_RAMB_REGION_4_5; \
+       uint32_t CM_SHAPER_RAMB_REGION_6_7; \
+       uint32_t CM_SHAPER_RAMB_REGION_8_9; \
+       uint32_t CM_SHAPER_RAMB_REGION_10_11; \
+       uint32_t CM_SHAPER_RAMB_REGION_12_13; \
+       uint32_t CM_SHAPER_RAMB_REGION_14_15; \
+       uint32_t CM_SHAPER_RAMB_REGION_16_17; \
+       uint32_t CM_SHAPER_RAMB_REGION_18_19; \
+       uint32_t CM_SHAPER_RAMB_REGION_20_21; \
+       uint32_t CM_SHAPER_RAMB_REGION_22_23; \
+       uint32_t CM_SHAPER_RAMB_REGION_24_25; \
+       uint32_t CM_SHAPER_RAMB_REGION_26_27; \
+       uint32_t CM_SHAPER_RAMB_REGION_28_29; \
+       uint32_t CM_SHAPER_RAMB_REGION_30_31; \
+       uint32_t CM_SHAPER_RAMB_REGION_32_33; \
+       uint32_t CM_SHAPER_RAMA_START_CNTL_B; \
+       uint32_t CM_SHAPER_RAMA_START_CNTL_G; \
+       uint32_t CM_SHAPER_RAMA_START_CNTL_R; \
+       uint32_t CM_SHAPER_RAMA_END_CNTL_B; \
+       uint32_t CM_SHAPER_RAMA_END_CNTL_G; \
+       uint32_t CM_SHAPER_RAMA_END_CNTL_R; \
+       uint32_t CM_SHAPER_RAMA_REGION_0_1; \
+       uint32_t CM_SHAPER_RAMA_REGION_2_3; \
+       uint32_t CM_SHAPER_RAMA_REGION_4_5; \
+       uint32_t CM_SHAPER_RAMA_REGION_6_7; \
+       uint32_t CM_SHAPER_RAMA_REGION_8_9; \
+       uint32_t CM_SHAPER_RAMA_REGION_10_11; \
+       uint32_t CM_SHAPER_RAMA_REGION_12_13; \
+       uint32_t CM_SHAPER_RAMA_REGION_14_15; \
+       uint32_t CM_SHAPER_RAMA_REGION_16_17; \
+       uint32_t CM_SHAPER_RAMA_REGION_18_19; \
+       uint32_t CM_SHAPER_RAMA_REGION_20_21; \
+       uint32_t CM_SHAPER_RAMA_REGION_22_23; \
+       uint32_t CM_SHAPER_RAMA_REGION_24_25; \
+       uint32_t CM_SHAPER_RAMA_REGION_26_27; \
+       uint32_t CM_SHAPER_RAMA_REGION_28_29; \
+       uint32_t CM_SHAPER_RAMA_REGION_30_31; \
+       uint32_t CM_SHAPER_RAMA_REGION_32_33; \
+       uint32_t CM_SHAPER_LUT_INDEX; \
+       uint32_t CM_SHAPER_LUT_DATA; \
+       uint32_t CM_ICSC_CONTROL; \
+       uint32_t CM_ICSC_C11_C12; \
+       uint32_t CM_ICSC_C33_C34; \
+       uint32_t CM_BNS_VALUES_R; \
+       uint32_t CM_BNS_VALUES_G; \
+       uint32_t CM_BNS_VALUES_B; \
+       uint32_t CM_DGAM_RAMB_START_CNTL_B; \
+       uint32_t CM_DGAM_RAMB_START_CNTL_G; \
+       uint32_t CM_DGAM_RAMB_START_CNTL_R; \
+       uint32_t CM_DGAM_RAMB_SLOPE_CNTL_B; \
+       uint32_t CM_DGAM_RAMB_SLOPE_CNTL_G; \
+       uint32_t CM_DGAM_RAMB_SLOPE_CNTL_R; \
+       uint32_t CM_DGAM_RAMB_END_CNTL1_B; \
+       uint32_t CM_DGAM_RAMB_END_CNTL2_B; \
+       uint32_t CM_DGAM_RAMB_END_CNTL1_G; \
+       uint32_t CM_DGAM_RAMB_END_CNTL2_G; \
+       uint32_t CM_DGAM_RAMB_END_CNTL1_R; \
+       uint32_t CM_DGAM_RAMB_END_CNTL2_R; \
+       uint32_t CM_DGAM_RAMB_REGION_0_1; \
+       uint32_t CM_DGAM_RAMB_REGION_14_15; \
+       uint32_t CM_DGAM_RAMA_START_CNTL_B; \
+       uint32_t CM_DGAM_RAMA_START_CNTL_G; \
+       uint32_t CM_DGAM_RAMA_START_CNTL_R; \
+       uint32_t CM_DGAM_RAMA_SLOPE_CNTL_B; \
+       uint32_t CM_DGAM_RAMA_SLOPE_CNTL_G; \
+       uint32_t CM_DGAM_RAMA_SLOPE_CNTL_R; \
+       uint32_t CM_DGAM_RAMA_END_CNTL1_B; \
+       uint32_t CM_DGAM_RAMA_END_CNTL2_B; \
+       uint32_t CM_DGAM_RAMA_END_CNTL1_G; \
+       uint32_t CM_DGAM_RAMA_END_CNTL2_G; \
+       uint32_t CM_DGAM_RAMA_END_CNTL1_R; \
+       uint32_t CM_DGAM_RAMA_END_CNTL2_R; \
+       uint32_t CM_DGAM_RAMA_REGION_0_1; \
+       uint32_t CM_DGAM_RAMA_REGION_14_15; \
+       uint32_t CM_DGAM_LUT_WRITE_EN_MASK; \
+       uint32_t CM_DGAM_LUT_INDEX; \
+       uint32_t CM_DGAM_LUT_DATA; \
+       uint32_t CM_CONTROL; \
+       uint32_t CM_DGAM_CONTROL; \
+       uint32_t CM_IGAM_CONTROL; \
+       uint32_t CM_IGAM_LUT_RW_CONTROL; \
+       uint32_t CM_IGAM_LUT_RW_INDEX; \
+       uint32_t CM_IGAM_LUT_SEQ_COLOR; \
+       uint32_t FORMAT_CONTROL; \
+       uint32_t CNVC_SURFACE_PIXEL_FORMAT; \
+       uint32_t CURSOR_CONTROL; \
+       uint32_t CURSOR0_CONTROL; \
+       uint32_t CURSOR0_COLOR0; \
+       uint32_t CURSOR0_COLOR1;
 
 struct dcn_dpp_registers {
-       uint32_t DSCL_EXT_OVERSCAN_LEFT_RIGHT;
-       uint32_t DSCL_EXT_OVERSCAN_TOP_BOTTOM;
-       uint32_t OTG_H_BLANK;
-       uint32_t OTG_V_BLANK;
-       uint32_t SCL_MODE;
-       uint32_t LB_DATA_FORMAT;
-       uint32_t LB_MEMORY_CTRL;
-       uint32_t DSCL_AUTOCAL;
-       uint32_t SCL_BLACK_OFFSET;
-       uint32_t SCL_TAP_CONTROL;
-       uint32_t SCL_COEF_RAM_TAP_SELECT;
-       uint32_t SCL_COEF_RAM_TAP_DATA;
-       uint32_t DSCL_2TAP_CONTROL;
-       uint32_t MPC_SIZE;
-       uint32_t SCL_HORZ_FILTER_SCALE_RATIO;
-       uint32_t SCL_VERT_FILTER_SCALE_RATIO;
-       uint32_t SCL_HORZ_FILTER_SCALE_RATIO_C;
-       uint32_t SCL_VERT_FILTER_SCALE_RATIO_C;
-       uint32_t SCL_HORZ_FILTER_INIT;
-       uint32_t SCL_HORZ_FILTER_INIT_C;
-       uint32_t SCL_VERT_FILTER_INIT;
-       uint32_t SCL_VERT_FILTER_INIT_BOT;
-       uint32_t SCL_VERT_FILTER_INIT_C;
-       uint32_t SCL_VERT_FILTER_INIT_BOT_C;
-       uint32_t RECOUT_START;
-       uint32_t RECOUT_SIZE;
-       uint32_t CM_GAMUT_REMAP_CONTROL;
-       uint32_t CM_GAMUT_REMAP_C11_C12;
-       uint32_t CM_GAMUT_REMAP_C33_C34;
-       uint32_t CM_COMA_C11_C12;
-       uint32_t CM_COMA_C33_C34;
-       uint32_t CM_COMB_C11_C12;
-       uint32_t CM_COMB_C33_C34;
-       uint32_t CM_OCSC_CONTROL;
-       uint32_t CM_OCSC_C11_C12;
-       uint32_t CM_OCSC_C33_C34;
-       uint32_t CM_MEM_PWR_CTRL;
-       uint32_t CM_RGAM_LUT_DATA;
-       uint32_t CM_RGAM_LUT_WRITE_EN_MASK;
-       uint32_t CM_RGAM_LUT_INDEX;
-       uint32_t CM_RGAM_RAMB_START_CNTL_B;
-       uint32_t CM_RGAM_RAMB_START_CNTL_G;
-       uint32_t CM_RGAM_RAMB_START_CNTL_R;
-       uint32_t CM_RGAM_RAMB_SLOPE_CNTL_B;
-       uint32_t CM_RGAM_RAMB_SLOPE_CNTL_G;
-       uint32_t CM_RGAM_RAMB_SLOPE_CNTL_R;
-       uint32_t CM_RGAM_RAMB_END_CNTL1_B;
-       uint32_t CM_RGAM_RAMB_END_CNTL2_B;
-       uint32_t CM_RGAM_RAMB_END_CNTL1_G;
-       uint32_t CM_RGAM_RAMB_END_CNTL2_G;
-       uint32_t CM_RGAM_RAMB_END_CNTL1_R;
-       uint32_t CM_RGAM_RAMB_END_CNTL2_R;
-       uint32_t CM_RGAM_RAMB_REGION_0_1;
-       uint32_t CM_RGAM_RAMB_REGION_32_33;
-       uint32_t CM_RGAM_RAMA_START_CNTL_B;
-       uint32_t CM_RGAM_RAMA_START_CNTL_G;
-       uint32_t CM_RGAM_RAMA_START_CNTL_R;
-       uint32_t CM_RGAM_RAMA_SLOPE_CNTL_B;
-       uint32_t CM_RGAM_RAMA_SLOPE_CNTL_G;
-       uint32_t CM_RGAM_RAMA_SLOPE_CNTL_R;
-       uint32_t CM_RGAM_RAMA_END_CNTL1_B;
-       uint32_t CM_RGAM_RAMA_END_CNTL2_B;
-       uint32_t CM_RGAM_RAMA_END_CNTL1_G;
-       uint32_t CM_RGAM_RAMA_END_CNTL2_G;
-       uint32_t CM_RGAM_RAMA_END_CNTL1_R;
-       uint32_t CM_RGAM_RAMA_END_CNTL2_R;
-       uint32_t CM_RGAM_RAMA_REGION_0_1;
-       uint32_t CM_RGAM_RAMA_REGION_32_33;
-       uint32_t CM_RGAM_CONTROL;
-       uint32_t CM_CMOUT_CONTROL;
-       uint32_t CM_BLNDGAM_LUT_WRITE_EN_MASK;
-       uint32_t CM_BLNDGAM_CONTROL;
-       uint32_t CM_BLNDGAM_RAMB_START_CNTL_B;
-       uint32_t CM_BLNDGAM_RAMB_START_CNTL_G;
-       uint32_t CM_BLNDGAM_RAMB_START_CNTL_R;
-       uint32_t CM_BLNDGAM_RAMB_SLOPE_CNTL_B;
-       uint32_t CM_BLNDGAM_RAMB_SLOPE_CNTL_G;
-       uint32_t CM_BLNDGAM_RAMB_SLOPE_CNTL_R;
-       uint32_t CM_BLNDGAM_RAMB_END_CNTL1_B;
-       uint32_t CM_BLNDGAM_RAMB_END_CNTL2_B;
-       uint32_t CM_BLNDGAM_RAMB_END_CNTL1_G;
-       uint32_t CM_BLNDGAM_RAMB_END_CNTL2_G;
-       uint32_t CM_BLNDGAM_RAMB_END_CNTL1_R;
-       uint32_t CM_BLNDGAM_RAMB_END_CNTL2_R;
-       uint32_t CM_BLNDGAM_RAMB_REGION_0_1;
-       uint32_t CM_BLNDGAM_RAMB_REGION_2_3;
-       uint32_t CM_BLNDGAM_RAMB_REGION_4_5;
-       uint32_t CM_BLNDGAM_RAMB_REGION_6_7;
-       uint32_t CM_BLNDGAM_RAMB_REGION_8_9;
-       uint32_t CM_BLNDGAM_RAMB_REGION_10_11;
-       uint32_t CM_BLNDGAM_RAMB_REGION_12_13;
-       uint32_t CM_BLNDGAM_RAMB_REGION_14_15;
-       uint32_t CM_BLNDGAM_RAMB_REGION_16_17;
-       uint32_t CM_BLNDGAM_RAMB_REGION_18_19;
-       uint32_t CM_BLNDGAM_RAMB_REGION_20_21;
-       uint32_t CM_BLNDGAM_RAMB_REGION_22_23;
-       uint32_t CM_BLNDGAM_RAMB_REGION_24_25;
-       uint32_t CM_BLNDGAM_RAMB_REGION_26_27;
-       uint32_t CM_BLNDGAM_RAMB_REGION_28_29;
-       uint32_t CM_BLNDGAM_RAMB_REGION_30_31;
-       uint32_t CM_BLNDGAM_RAMB_REGION_32_33;
-       uint32_t CM_BLNDGAM_RAMA_START_CNTL_B;
-       uint32_t CM_BLNDGAM_RAMA_START_CNTL_G;
-       uint32_t CM_BLNDGAM_RAMA_START_CNTL_R;
-       uint32_t CM_BLNDGAM_RAMA_SLOPE_CNTL_B;
-       uint32_t CM_BLNDGAM_RAMA_SLOPE_CNTL_G;
-       uint32_t CM_BLNDGAM_RAMA_SLOPE_CNTL_R;
-       uint32_t CM_BLNDGAM_RAMA_END_CNTL1_B;
-       uint32_t CM_BLNDGAM_RAMA_END_CNTL2_B;
-       uint32_t CM_BLNDGAM_RAMA_END_CNTL1_G;
-       uint32_t CM_BLNDGAM_RAMA_END_CNTL2_G;
-       uint32_t CM_BLNDGAM_RAMA_END_CNTL1_R;
-       uint32_t CM_BLNDGAM_RAMA_END_CNTL2_R;
-       uint32_t CM_BLNDGAM_RAMA_REGION_0_1;
-       uint32_t CM_BLNDGAM_RAMA_REGION_2_3;
-       uint32_t CM_BLNDGAM_RAMA_REGION_4_5;
-       uint32_t CM_BLNDGAM_RAMA_REGION_6_7;
-       uint32_t CM_BLNDGAM_RAMA_REGION_8_9;
-       uint32_t CM_BLNDGAM_RAMA_REGION_10_11;
-       uint32_t CM_BLNDGAM_RAMA_REGION_12_13;
-       uint32_t CM_BLNDGAM_RAMA_REGION_14_15;
-       uint32_t CM_BLNDGAM_RAMA_REGION_16_17;
-       uint32_t CM_BLNDGAM_RAMA_REGION_18_19;
-       uint32_t CM_BLNDGAM_RAMA_REGION_20_21;
-       uint32_t CM_BLNDGAM_RAMA_REGION_22_23;
-       uint32_t CM_BLNDGAM_RAMA_REGION_24_25;
-       uint32_t CM_BLNDGAM_RAMA_REGION_26_27;
-       uint32_t CM_BLNDGAM_RAMA_REGION_28_29;
-       uint32_t CM_BLNDGAM_RAMA_REGION_30_31;
-       uint32_t CM_BLNDGAM_RAMA_REGION_32_33;
-       uint32_t CM_BLNDGAM_LUT_INDEX;
-       uint32_t CM_BLNDGAM_LUT_DATA;
-       uint32_t CM_3DLUT_MODE;
-       uint32_t CM_3DLUT_INDEX;
-       uint32_t CM_3DLUT_DATA;
-       uint32_t CM_3DLUT_DATA_30BIT;
-       uint32_t CM_3DLUT_READ_WRITE_CONTROL;
-       uint32_t CM_SHAPER_LUT_WRITE_EN_MASK;
-       uint32_t CM_SHAPER_CONTROL;
-       uint32_t CM_SHAPER_RAMB_START_CNTL_B;
-       uint32_t CM_SHAPER_RAMB_START_CNTL_G;
-       uint32_t CM_SHAPER_RAMB_START_CNTL_R;
-       uint32_t CM_SHAPER_RAMB_END_CNTL_B;
-       uint32_t CM_SHAPER_RAMB_END_CNTL_G;
-       uint32_t CM_SHAPER_RAMB_END_CNTL_R;
-       uint32_t CM_SHAPER_RAMB_REGION_0_1;
-       uint32_t CM_SHAPER_RAMB_REGION_2_3;
-       uint32_t CM_SHAPER_RAMB_REGION_4_5;
-       uint32_t CM_SHAPER_RAMB_REGION_6_7;
-       uint32_t CM_SHAPER_RAMB_REGION_8_9;
-       uint32_t CM_SHAPER_RAMB_REGION_10_11;
-       uint32_t CM_SHAPER_RAMB_REGION_12_13;
-       uint32_t CM_SHAPER_RAMB_REGION_14_15;
-       uint32_t CM_SHAPER_RAMB_REGION_16_17;
-       uint32_t CM_SHAPER_RAMB_REGION_18_19;
-       uint32_t CM_SHAPER_RAMB_REGION_20_21;
-       uint32_t CM_SHAPER_RAMB_REGION_22_23;
-       uint32_t CM_SHAPER_RAMB_REGION_24_25;
-       uint32_t CM_SHAPER_RAMB_REGION_26_27;
-       uint32_t CM_SHAPER_RAMB_REGION_28_29;
-       uint32_t CM_SHAPER_RAMB_REGION_30_31;
-       uint32_t CM_SHAPER_RAMB_REGION_32_33;
-       uint32_t CM_SHAPER_RAMA_START_CNTL_B;
-       uint32_t CM_SHAPER_RAMA_START_CNTL_G;
-       uint32_t CM_SHAPER_RAMA_START_CNTL_R;
-       uint32_t CM_SHAPER_RAMA_END_CNTL_B;
-       uint32_t CM_SHAPER_RAMA_END_CNTL_G;
-       uint32_t CM_SHAPER_RAMA_END_CNTL_R;
-       uint32_t CM_SHAPER_RAMA_REGION_0_1;
-       uint32_t CM_SHAPER_RAMA_REGION_2_3;
-       uint32_t CM_SHAPER_RAMA_REGION_4_5;
-       uint32_t CM_SHAPER_RAMA_REGION_6_7;
-       uint32_t CM_SHAPER_RAMA_REGION_8_9;
-       uint32_t CM_SHAPER_RAMA_REGION_10_11;
-       uint32_t CM_SHAPER_RAMA_REGION_12_13;
-       uint32_t CM_SHAPER_RAMA_REGION_14_15;
-       uint32_t CM_SHAPER_RAMA_REGION_16_17;
-       uint32_t CM_SHAPER_RAMA_REGION_18_19;
-       uint32_t CM_SHAPER_RAMA_REGION_20_21;
-       uint32_t CM_SHAPER_RAMA_REGION_22_23;
-       uint32_t CM_SHAPER_RAMA_REGION_24_25;
-       uint32_t CM_SHAPER_RAMA_REGION_26_27;
-       uint32_t CM_SHAPER_RAMA_REGION_28_29;
-       uint32_t CM_SHAPER_RAMA_REGION_30_31;
-       uint32_t CM_SHAPER_RAMA_REGION_32_33;
-       uint32_t CM_SHAPER_LUT_INDEX;
-       uint32_t CM_SHAPER_LUT_DATA;
-       uint32_t CM_ICSC_CONTROL;
-       uint32_t CM_ICSC_C11_C12;
-       uint32_t CM_ICSC_C33_C34;
-       uint32_t CM_BNS_VALUES_R;
-       uint32_t CM_BNS_VALUES_G;
-       uint32_t CM_BNS_VALUES_B;
-       uint32_t CM_DGAM_RAMB_START_CNTL_B;
-       uint32_t CM_DGAM_RAMB_START_CNTL_G;
-       uint32_t CM_DGAM_RAMB_START_CNTL_R;
-       uint32_t CM_DGAM_RAMB_SLOPE_CNTL_B;
-       uint32_t CM_DGAM_RAMB_SLOPE_CNTL_G;
-       uint32_t CM_DGAM_RAMB_SLOPE_CNTL_R;
-       uint32_t CM_DGAM_RAMB_END_CNTL1_B;
-       uint32_t CM_DGAM_RAMB_END_CNTL2_B;
-       uint32_t CM_DGAM_RAMB_END_CNTL1_G;
-       uint32_t CM_DGAM_RAMB_END_CNTL2_G;
-       uint32_t CM_DGAM_RAMB_END_CNTL1_R;
-       uint32_t CM_DGAM_RAMB_END_CNTL2_R;
-       uint32_t CM_DGAM_RAMB_REGION_0_1;
-       uint32_t CM_DGAM_RAMB_REGION_14_15;
-       uint32_t CM_DGAM_RAMA_START_CNTL_B;
-       uint32_t CM_DGAM_RAMA_START_CNTL_G;
-       uint32_t CM_DGAM_RAMA_START_CNTL_R;
-       uint32_t CM_DGAM_RAMA_SLOPE_CNTL_B;
-       uint32_t CM_DGAM_RAMA_SLOPE_CNTL_G;
-       uint32_t CM_DGAM_RAMA_SLOPE_CNTL_R;
-       uint32_t CM_DGAM_RAMA_END_CNTL1_B;
-       uint32_t CM_DGAM_RAMA_END_CNTL2_B;
-       uint32_t CM_DGAM_RAMA_END_CNTL1_G;
-       uint32_t CM_DGAM_RAMA_END_CNTL2_G;
-       uint32_t CM_DGAM_RAMA_END_CNTL1_R;
-       uint32_t CM_DGAM_RAMA_END_CNTL2_R;
-       uint32_t CM_DGAM_RAMA_REGION_0_1;
-       uint32_t CM_DGAM_RAMA_REGION_14_15;
-       uint32_t CM_DGAM_LUT_WRITE_EN_MASK;
-       uint32_t CM_DGAM_LUT_INDEX;
-       uint32_t CM_DGAM_LUT_DATA;
-       uint32_t CM_CONTROL;
-       uint32_t CM_DGAM_CONTROL;
-       uint32_t CM_IGAM_CONTROL;
-       uint32_t CM_IGAM_LUT_RW_CONTROL;
-       uint32_t CM_IGAM_LUT_RW_INDEX;
-       uint32_t CM_IGAM_LUT_SEQ_COLOR;
-       uint32_t FORMAT_CONTROL;
-       uint32_t CNVC_SURFACE_PIXEL_FORMAT;
-       uint32_t CURSOR_CONTROL;
-       uint32_t CURSOR0_CONTROL;
-       uint32_t CURSOR0_COLOR0;
-       uint32_t CURSOR0_COLOR1;
+       DPP_COMMON_REG_VARIABLE_LIST
 };
 
 struct dcn10_dpp {

diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h
index ccb4896975c2430c9c00cab50ced81250b3d2ab4..6ccc90ffb0f286890ea06d53bc4d6594ac1a253a 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h
@@ -122,7 +122,7 @@ struct dpp_funcs {
 
        void (*set_cursor_attributes)(
                        struct dpp *dpp_base,
-                       const struct dc_cursor_attributes *attr);
+                       enum dc_cursor_color_format color_format);
 
        void (*set_cursor_position)(
                        struct dpp *dpp_base,