riscv, bpf: Try RVC for reg move within BPF_CMPXCHG JIT

We could try to emit compressed insn for reg move operation during CMPXCHG
JIT, the instruction compression has no impact on the jump offsets of
following forward and backward jump instructions.

Signed-off-by: Xiao Wang <xiao.w.wang@intel.com>
Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>
Acked-by: Björn Töpel <bjorn@kernel.org>
Link: https://lore.kernel.org/bpf/20240519050507.2217791-1-xiao.w.wang@intel.com

diff --git a/arch/riscv/net/bpf_jit_comp64.c b/arch/riscv/net/bpf_jit_comp64.c
index c21a0ff234158d0d8418a6e9814fe994756e2988..2bc4c14ea59a5d77c8a3cb362f05738137eb6c0e 100644 (file)
--- a/arch/riscv/net/bpf_jit_comp64.c
+++ b/arch/riscv/net/bpf_jit_comp64.c
@@ -537,8 +537,10 @@ static void emit_atomic(u8 rd, u8 rs, s16 off, s32 imm, bool is64,
        /* r0 = atomic_cmpxchg(dst_reg + off16, r0, src_reg); */
        case BPF_CMPXCHG:
                r0 = bpf_to_rv_reg(BPF_REG_0, ctx);
-               emit(is64 ? rv_addi(RV_REG_T2, r0, 0) :
-                    rv_addiw(RV_REG_T2, r0, 0), ctx);
+               if (is64)
+                       emit_mv(RV_REG_T2, r0, ctx);
+               else
+                       emit_addiw(RV_REG_T2, r0, 0, ctx);
                emit(is64 ? rv_lr_d(r0, 0, rd, 0, 0) :
                     rv_lr_w(r0, 0, rd, 0, 0), ctx);
                jmp_offset = ninsns_rvoff(8);