phy: qcom-qmp: pcs: Add missing v6 N4 register offsets

The new X1E80100 SoC bumps up the HW version of QMP phy to v6 N4 for
combo USB and DP PHY.  Currently, the X1E80100 uses the pure V6 PCS
register offsets, which are different. Add the offsets so the
mentioned platform can be fixed later on. Add the new PCS offsets
in a dedicated header file.

Fixes: d7b3579f84f7 ("phy: qcom-qmp-combo: Add x1e80100 USB/DP combo phys")
Co-developed-by: Kuogee Hsieh <quic_khsieh@quicinc.com>
Signed-off-by: Kuogee Hsieh <quic_khsieh@quicinc.com>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240527-x1e80100-phy-qualcomm-combo-fix-dp-v1-2-be8a0b882117@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6-n4.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6-n4.h
new file mode 100644 (file)
index 0000000..b302471
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6-n4.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2023, Linaro Limited
+ */
+
+#ifndef QCOM_PHY_QMP_PCS_V6_N4_H_
+#define QCOM_PHY_QMP_PCS_V6_N4_H_
+
+/* Only for QMP V6 N4 PHY - USB/PCIe PCS registers */
+#define QPHY_V6_N4_PCS_SW_RESET                        0x000
+#define QPHY_V6_N4_PCS_PCS_STATUS1             0x014
+#define QPHY_V6_N4_PCS_POWER_DOWN_CONTROL      0x040
+#define QPHY_V6_N4_PCS_START_CONTROL           0x044
+#define QPHY_V6_N4_PCS_POWER_STATE_CONFIG1     0x090
+#define QPHY_V6_N4_PCS_LOCK_DETECT_CONFIG1     0x0c4
+#define QPHY_V6_N4_PCS_LOCK_DETECT_CONFIG2     0x0c8
+#define QPHY_V6_N4_PCS_LOCK_DETECT_CONFIG3     0x0cc
+#define QPHY_V6_N4_PCS_LOCK_DETECT_CONFIG6     0x0d8
+#define QPHY_V6_N4_PCS_REFGEN_REQ_CONFIG1      0x0dc
+#define QPHY_V6_N4_PCS_RX_SIGDET_LVL           0x188
+#define QPHY_V6_N4_PCS_RCVR_DTCT_DLY_P1U2_L    0x190
+#define QPHY_V6_N4_PCS_RCVR_DTCT_DLY_P1U2_H    0x194
+#define QPHY_V6_N4_PCS_RATE_SLEW_CNTRL1                0x198
+#define QPHY_V6_N4_PCS_RX_CONFIG               0x1b0
+#define QPHY_V6_N4_PCS_ALIGN_DETECT_CONFIG1    0x1c0
+#define QPHY_V6_N4_PCS_ALIGN_DETECT_CONFIG2    0x1c4
+#define QPHY_V6_N4_PCS_PCS_TX_RX_CONFIG                0x1d0
+#define QPHY_V6_N4_PCS_EQ_CONFIG1              0x1dc
+#define QPHY_V6_N4_PCS_EQ_CONFIG2              0x1e0
+#define QPHY_V6_N4_PCS_EQ_CONFIG5              0x1ec
+
+#endif