rt2x00: Unify GPIO register field namings
authorGertjan van Wingerde <gwingerde@gmail.com>
Fri, 31 Aug 2012 17:22:13 +0000 (19:22 +0200)
committerJohn W. Linville <linville@tuxdriver.com>
Fri, 7 Sep 2012 19:08:40 +0000 (15:08 -0400)
The various rt2x00 drivers use different methods to name the different
GPIO register fields indicating the GPIO pin value and the fields
indicating the direction.
Start using a unified naming scheme for the GPIO register fields:
- <csr>_VAL<x> for fields indicating the GPIO pin value.
- <csr>_DIR<x> for fields indicating the GPIO pin direction.

Signed-off-by: Gertjan van Wingerde <gwingerde@gmail.com>
Acked-by: Ivo Van Doorn <ivdoorn@gmail.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
14 files changed:
drivers/net/wireless/rt2x00/rt2400pci.c
drivers/net/wireless/rt2x00/rt2400pci.h
drivers/net/wireless/rt2x00/rt2500pci.c
drivers/net/wireless/rt2x00/rt2500pci.h
drivers/net/wireless/rt2x00/rt2500usb.c
drivers/net/wireless/rt2x00/rt2500usb.h
drivers/net/wireless/rt2x00/rt2800.h
drivers/net/wireless/rt2x00/rt2800lib.c
drivers/net/wireless/rt2x00/rt2800pci.c
drivers/net/wireless/rt2x00/rt2800usb.c
drivers/net/wireless/rt2x00/rt61pci.c
drivers/net/wireless/rt2x00/rt61pci.h
drivers/net/wireless/rt2x00/rt73usb.c
drivers/net/wireless/rt2x00/rt73usb.h

index 64328af496f598bb3280784b6d2adfd25ec5cc70..6458ab87717b625669074e9a637bf138e8e57af0 100644 (file)
@@ -205,7 +205,7 @@ static int rt2400pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
        u32 reg;
 
        rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg);
-       return rt2x00_get_field32(reg, GPIOCSR_BIT0);
+       return rt2x00_get_field32(reg, GPIOCSR_VAL0);
 }
 
 #ifdef CONFIG_RT2X00_LIB_LEDS
@@ -1629,7 +1629,7 @@ static int rt2400pci_probe_hw(struct rt2x00_dev *rt2x00dev)
         * rfkill switch GPIO pin correctly.
         */
        rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg);
-       rt2x00_set_field32(&reg, GPIOCSR_BIT8, 1);
+       rt2x00_set_field32(&reg, GPIOCSR_DIR0, 1);
        rt2x00pci_register_write(rt2x00dev, GPIOCSR, reg);
 
        /*
index 9d78a53ac61a3327ecc707c50a93134e29ec847f..e4b07f0aa3cc0bfd955c1cebfcc1e1443065a4f9 100644 (file)
 
 /*
  * GPIOCSR: GPIO control register.
+ *     GPIOCSR_VALx: Actual GPIO pin x value
+ *     GPIOCSR_DIRx: GPIO direction: 0 = output; 1 = input
  */
 #define GPIOCSR                                0x0120
-#define GPIOCSR_BIT0                   FIELD32(0x00000001)
-#define GPIOCSR_BIT1                   FIELD32(0x00000002)
-#define GPIOCSR_BIT2                   FIELD32(0x00000004)
-#define GPIOCSR_BIT3                   FIELD32(0x00000008)
-#define GPIOCSR_BIT4                   FIELD32(0x00000010)
-#define GPIOCSR_BIT5                   FIELD32(0x00000020)
-#define GPIOCSR_BIT6                   FIELD32(0x00000040)
-#define GPIOCSR_BIT7                   FIELD32(0x00000080)
-#define GPIOCSR_BIT8                   FIELD32(0x00000100)
-#define GPIOCSR_BIT9                   FIELD32(0x00000200)
-#define GPIOCSR_BIT10                  FIELD32(0x00000400)
-#define GPIOCSR_BIT11                  FIELD32(0x00000800)
-#define GPIOCSR_BIT12                  FIELD32(0x00001000)
-#define GPIOCSR_BIT13                  FIELD32(0x00002000)
-#define GPIOCSR_BIT14                  FIELD32(0x00004000)
-#define GPIOCSR_BIT15                  FIELD32(0x00008000)
+#define GPIOCSR_VAL0                   FIELD32(0x00000001)
+#define GPIOCSR_VAL1                   FIELD32(0x00000002)
+#define GPIOCSR_VAL2                   FIELD32(0x00000004)
+#define GPIOCSR_VAL3                   FIELD32(0x00000008)
+#define GPIOCSR_VAL4                   FIELD32(0x00000010)
+#define GPIOCSR_VAL5                   FIELD32(0x00000020)
+#define GPIOCSR_VAL6                   FIELD32(0x00000040)
+#define GPIOCSR_VAL7                   FIELD32(0x00000080)
+#define GPIOCSR_DIR0                   FIELD32(0x00000100)
+#define GPIOCSR_DIR1                   FIELD32(0x00000200)
+#define GPIOCSR_DIR2                   FIELD32(0x00000400)
+#define GPIOCSR_DIR3                   FIELD32(0x00000800)
+#define GPIOCSR_DIR4                   FIELD32(0x00001000)
+#define GPIOCSR_DIR5                   FIELD32(0x00002000)
+#define GPIOCSR_DIR6                   FIELD32(0x00004000)
+#define GPIOCSR_DIR7                   FIELD32(0x00008000)
 
 /*
  * BBPPCSR: BBP Pin control register.
index 3de0406735f6b7347b46cdf2305e413aaa17256d..68bca1456cdaf39433d361a767e78010100e29ce 100644 (file)
@@ -205,7 +205,7 @@ static int rt2500pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
        u32 reg;
 
        rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg);
-       return rt2x00_get_field32(reg, GPIOCSR_BIT0);
+       return rt2x00_get_field32(reg, GPIOCSR_VAL0);
 }
 
 #ifdef CONFIG_RT2X00_LIB_LEDS
index 2aad7ba8a10083547c8e39d4cba5dc77dcbc42d7..9c10068e4987a384019301542f664bd44f1b130a 100644 (file)
 
 /*
  * GPIOCSR: GPIO control register.
+ *     GPIOCSR_VALx: GPIO value
+ *     GPIOCSR_DIRx: GPIO direction: 0 = output; 1 = input
  */
 #define GPIOCSR                                0x0120
-#define GPIOCSR_BIT0                   FIELD32(0x00000001)
-#define GPIOCSR_BIT1                   FIELD32(0x00000002)
-#define GPIOCSR_BIT2                   FIELD32(0x00000004)
-#define GPIOCSR_BIT3                   FIELD32(0x00000008)
-#define GPIOCSR_BIT4                   FIELD32(0x00000010)
-#define GPIOCSR_BIT5                   FIELD32(0x00000020)
-#define GPIOCSR_BIT6                   FIELD32(0x00000040)
-#define GPIOCSR_BIT7                   FIELD32(0x00000080)
+#define GPIOCSR_VAL0                   FIELD32(0x00000001)
+#define GPIOCSR_VAL1                   FIELD32(0x00000002)
+#define GPIOCSR_VAL2                   FIELD32(0x00000004)
+#define GPIOCSR_VAL3                   FIELD32(0x00000008)
+#define GPIOCSR_VAL4                   FIELD32(0x00000010)
+#define GPIOCSR_VAL5                   FIELD32(0x00000020)
+#define GPIOCSR_VAL6                   FIELD32(0x00000040)
+#define GPIOCSR_VAL7                   FIELD32(0x00000080)
 #define GPIOCSR_DIR0                   FIELD32(0x00000100)
 #define GPIOCSR_DIR1                   FIELD32(0x00000200)
 #define GPIOCSR_DIR2                   FIELD32(0x00000400)
index 89fee311d8fda5ad07ae5ecd50fae567232aa35d..f95b5516c50aadaa5172bf25e0b41ba31b4e6b03 100644 (file)
@@ -283,7 +283,7 @@ static int rt2500usb_rfkill_poll(struct rt2x00_dev *rt2x00dev)
        u16 reg;
 
        rt2500usb_register_read(rt2x00dev, MAC_CSR19, &reg);
-       return rt2x00_get_field16(reg, MAC_CSR19_BIT7);
+       return rt2x00_get_field16(reg, MAC_CSR19_VAL7);
 }
 
 #ifdef CONFIG_RT2X00_LIB_LEDS
@@ -1786,7 +1786,7 @@ static int rt2500usb_probe_hw(struct rt2x00_dev *rt2x00dev)
         * rfkill switch GPIO pin correctly.
         */
        rt2500usb_register_read(rt2x00dev, MAC_CSR19, &reg);
-       rt2x00_set_field16(&reg, MAC_CSR19_BIT8, 0);
+       rt2x00_set_field16(&reg, MAC_CSR19_DIR0, 0);
        rt2500usb_register_write(rt2x00dev, MAC_CSR19, reg);
 
        /*
index 9652300b6f9c8a604306ac88ef0196d07e2482fa..1b91a4cef9652c22fe336c2c889ec300d04d685f 100644 (file)
 
 /*
  * MAC_CSR19: GPIO control register.
+ *     MAC_CSR19_VALx: GPIO value
+ *     MAC_CSR19_DIRx: GPIO direction: 0 = input; 1 = output
  */
 #define MAC_CSR19                      0x0426
-#define MAC_CSR19_BIT0                 FIELD16(0x0001)
-#define MAC_CSR19_BIT1                 FIELD16(0x0002)
-#define MAC_CSR19_BIT2                 FIELD16(0x0004)
-#define MAC_CSR19_BIT3                 FIELD16(0x0008)
-#define MAC_CSR19_BIT4                 FIELD16(0x0010)
-#define MAC_CSR19_BIT5                 FIELD16(0x0020)
-#define MAC_CSR19_BIT6                 FIELD16(0x0040)
-#define MAC_CSR19_BIT7                 FIELD16(0x0080)
-#define MAC_CSR19_BIT8                 FIELD16(0x0100)
-#define MAC_CSR19_BIT9                 FIELD16(0x0200)
-#define MAC_CSR19_BIT10                        FIELD16(0x0400)
-#define MAC_CSR19_BIT11                        FIELD16(0x0800)
-#define MAC_CSR19_BIT12                        FIELD16(0x1000)
-#define MAC_CSR19_BIT13                        FIELD16(0x2000)
-#define MAC_CSR19_BIT14                        FIELD16(0x4000)
-#define MAC_CSR19_BIT15                        FIELD16(0x8000)
+#define MAC_CSR19_VAL0                 FIELD16(0x0001)
+#define MAC_CSR19_VAL1                 FIELD16(0x0002)
+#define MAC_CSR19_VAL2                 FIELD16(0x0004)
+#define MAC_CSR19_VAL3                 FIELD16(0x0008)
+#define MAC_CSR19_VAL4                 FIELD16(0x0010)
+#define MAC_CSR19_VAL5                 FIELD16(0x0020)
+#define MAC_CSR19_VAL6                 FIELD16(0x0040)
+#define MAC_CSR19_VAL7                 FIELD16(0x0080)
+#define MAC_CSR19_DIR0                 FIELD16(0x0100)
+#define MAC_CSR19_DIR1                 FIELD16(0x0200)
+#define MAC_CSR19_DIR2                 FIELD16(0x0400)
+#define MAC_CSR19_DIR3                 FIELD16(0x0800)
+#define MAC_CSR19_DIR4                 FIELD16(0x1000)
+#define MAC_CSR19_DIR5                 FIELD16(0x2000)
+#define MAC_CSR19_DIR6                 FIELD16(0x4000)
+#define MAC_CSR19_DIR7                 FIELD16(0x8000)
 
 /*
  * MAC_CSR20: LED control register.
index a838e17db45cf433ddc28032e96c7c9ec6feb3dc..e13916f180019c8c86dcb77bac4b54c4272cbd58 100644 (file)
 #define WMM_TXOP1_CFG_AC3TXOP          FIELD32(0xffff0000)
 
 /*
- * GPIO_CTRL_CFG:
- * GPIOD: GPIO direction, 0: Output, 1: Input
- */
-#define GPIO_CTRL_CFG                  0x0228
-#define GPIO_CTRL_CFG_BIT0             FIELD32(0x00000001)
-#define GPIO_CTRL_CFG_BIT1             FIELD32(0x00000002)
-#define GPIO_CTRL_CFG_BIT2             FIELD32(0x00000004)
-#define GPIO_CTRL_CFG_BIT3             FIELD32(0x00000008)
-#define GPIO_CTRL_CFG_BIT4             FIELD32(0x00000010)
-#define GPIO_CTRL_CFG_BIT5             FIELD32(0x00000020)
-#define GPIO_CTRL_CFG_BIT6             FIELD32(0x00000040)
-#define GPIO_CTRL_CFG_BIT7             FIELD32(0x00000080)
-#define GPIO_CTRL_CFG_GPIOD_BIT0       FIELD32(0x00000100)
-#define GPIO_CTRL_CFG_GPIOD_BIT1       FIELD32(0x00000200)
-#define GPIO_CTRL_CFG_GPIOD_BIT2       FIELD32(0x00000400)
-#define GPIO_CTRL_CFG_GPIOD_BIT3       FIELD32(0x00000800)
-#define GPIO_CTRL_CFG_GPIOD_BIT4       FIELD32(0x00001000)
-#define GPIO_CTRL_CFG_GPIOD_BIT5       FIELD32(0x00002000)
-#define GPIO_CTRL_CFG_GPIOD_BIT6       FIELD32(0x00004000)
-#define GPIO_CTRL_CFG_GPIOD_BIT7       FIELD32(0x00008000)
-#define GPIO_CTRL_CFG_BIT8             FIELD32(0x00010000)
-#define GPIO_CTRL_CFG_BIT9             FIELD32(0x00020000)
-#define GPIO_CTRL_CFG_BIT10            FIELD32(0x00040000)
-#define GPIO_CTRL_CFG_GPIOD_BIT8       FIELD32(0x01000000)
-#define GPIO_CTRL_CFG_GPIOD_BIT9       FIELD32(0x02000000)
-#define GPIO_CTRL_CFG_GPIOD_BIT10      FIELD32(0x04000000)
+ * GPIO_CTRL:
+ *     GPIO_CTRL_VALx: GPIO value
+ *     GPIO_CTRL_DIRx: GPIO direction: 0 = output; 1 = input
+ */
+#define GPIO_CTRL                      0x0228
+#define GPIO_CTRL_VAL0                 FIELD32(0x00000001)
+#define GPIO_CTRL_VAL1                 FIELD32(0x00000002)
+#define GPIO_CTRL_VAL2                 FIELD32(0x00000004)
+#define GPIO_CTRL_VAL3                 FIELD32(0x00000008)
+#define GPIO_CTRL_VAL4                 FIELD32(0x00000010)
+#define GPIO_CTRL_VAL5                 FIELD32(0x00000020)
+#define GPIO_CTRL_VAL6                 FIELD32(0x00000040)
+#define GPIO_CTRL_VAL7                 FIELD32(0x00000080)
+#define GPIO_CTRL_DIR0                 FIELD32(0x00000100)
+#define GPIO_CTRL_DIR1                 FIELD32(0x00000200)
+#define GPIO_CTRL_DIR2                 FIELD32(0x00000400)
+#define GPIO_CTRL_DIR3                 FIELD32(0x00000800)
+#define GPIO_CTRL_DIR4                 FIELD32(0x00001000)
+#define GPIO_CTRL_DIR5                 FIELD32(0x00002000)
+#define GPIO_CTRL_DIR6                 FIELD32(0x00004000)
+#define GPIO_CTRL_DIR7                 FIELD32(0x00008000)
+#define GPIO_CTRL_VAL8                 FIELD32(0x00010000)
+#define GPIO_CTRL_VAL9                 FIELD32(0x00020000)
+#define GPIO_CTRL_VAL10                        FIELD32(0x00040000)
+#define GPIO_CTRL_DIR8                 FIELD32(0x01000000)
+#define GPIO_CTRL_DIR9                 FIELD32(0x02000000)
+#define GPIO_CTRL_DIR10                        FIELD32(0x04000000)
 
 /*
  * MCU_CMD_CFG
index b93516d832fb5603e4bb3d287a4770c0c8de06ad..58fc1d9bacd66452ad85a33e33ccf6b3fd23f83a 100644 (file)
@@ -923,8 +923,8 @@ int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
                rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
                return rt2x00_get_field32(reg, WLAN_GPIO_IN_BIT0);
        } else {
-               rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
-               return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
+               rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
+               return rt2x00_get_field32(reg, GPIO_CTRL_VAL2);
        }
 }
 EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
@@ -1570,10 +1570,10 @@ static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev,
                rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff,
                                   eesk_pin, 0);
 
-       rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
-       rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT3, 0);
-       rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT3, gpio_bit3);
-       rt2800_register_write(rt2x00dev, GPIO_CTRL_CFG, reg);
+       rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
+       rt2x00_set_field32(&reg, GPIO_CTRL_DIR3, 0);
+       rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, gpio_bit3);
+       rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
 }
 
 void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
@@ -1995,13 +1995,13 @@ static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev,
                rt2800_rfcsr_write(rt2x00dev, 29, 0x9f);
        }
 
-       rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
-       rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT7, 0);
+       rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
+       rt2x00_set_field32(&reg, GPIO_CTRL_DIR7, 0);
        if (rf->channel <= 14)
-               rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT7, 1);
+               rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 1);
        else
-               rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT7, 0);
-       rt2800_register_write(rt2x00dev, GPIO_CTRL_CFG, reg);
+               rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 0);
+       rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
 
        rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
        rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
@@ -3587,16 +3587,16 @@ static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
                if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
                        u32 reg;
 
-                       rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
-                       rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT3, 0);
-                       rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT6, 0);
-                       rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT3, 0);
-                       rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT6, 0);
+                       rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
+                       rt2x00_set_field32(&reg, GPIO_CTRL_DIR3, 0);
+                       rt2x00_set_field32(&reg, GPIO_CTRL_DIR6, 0);
+                       rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, 0);
+                       rt2x00_set_field32(&reg, GPIO_CTRL_VAL6, 0);
                        if (ant == 0)
-                               rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT3, 1);
+                               rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, 1);
                        else if (ant == 1)
-                               rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT6, 1);
-                       rt2800_register_write(rt2x00dev, GPIO_CTRL_CFG, reg);
+                               rt2x00_set_field32(&reg, GPIO_CTRL_VAL6, 1);
+                       rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
                }
 
                /* This chip has hardware antenna diversity*/
index 4765bbd654cdcfeea617c84f9c755db05409600d..09655409455429edf78cca762774e0e767f4dd7b 100644 (file)
@@ -1000,9 +1000,9 @@ static int rt2800pci_probe_hw(struct rt2x00_dev *rt2x00dev)
         * Enable rfkill polling by setting GPIO direction of the
         * rfkill switch GPIO pin correctly.
         */
-       rt2x00pci_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
-       rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT2, 1);
-       rt2x00pci_register_write(rt2x00dev, GPIO_CTRL_CFG, reg);
+       rt2x00pci_register_read(rt2x00dev, GPIO_CTRL, &reg);
+       rt2x00_set_field32(&reg, GPIO_CTRL_DIR2, 1);
+       rt2x00pci_register_write(rt2x00dev, GPIO_CTRL, reg);
 
        /*
         * Initialize hw specifications.
index 6b4226b716187ea037d2a1c84e012806649e8816..b13b3142996a1cc3851f889cc4f3beef7bb2937a 100644 (file)
@@ -761,9 +761,9 @@ static int rt2800usb_probe_hw(struct rt2x00_dev *rt2x00dev)
         * Enable rfkill polling by setting GPIO direction of the
         * rfkill switch GPIO pin correctly.
         */
-       rt2x00usb_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
-       rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT2, 1);
-       rt2x00usb_register_write(rt2x00dev, GPIO_CTRL_CFG, reg);
+       rt2x00usb_register_read(rt2x00dev, GPIO_CTRL, &reg);
+       rt2x00_set_field32(&reg, GPIO_CTRL_DIR2, 1);
+       rt2x00usb_register_write(rt2x00dev, GPIO_CTRL, reg);
 
        /*
         * Initialize hw specifications.
index b8ec96163922a11711a3d6800b9556052c1386fc..2673e058caaf62b7a3540f6f4b2156ba2a5e1ecf 100644 (file)
@@ -243,7 +243,7 @@ static int rt61pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
        u32 reg;
 
        rt2x00pci_register_read(rt2x00dev, MAC_CSR13, &reg);
-       return rt2x00_get_field32(reg, MAC_CSR13_BIT5);
+       return rt2x00_get_field32(reg, MAC_CSR13_VAL5);
 }
 
 #ifdef CONFIG_RT2X00_LIB_LEDS
@@ -715,11 +715,11 @@ static void rt61pci_config_antenna_2529_rx(struct rt2x00_dev *rt2x00dev,
 
        rt2x00pci_register_read(rt2x00dev, MAC_CSR13, &reg);
 
-       rt2x00_set_field32(&reg, MAC_CSR13_BIT4, p1);
-       rt2x00_set_field32(&reg, MAC_CSR13_BIT12, 0);
+       rt2x00_set_field32(&reg, MAC_CSR13_DIR4, 0);
+       rt2x00_set_field32(&reg, MAC_CSR13_VAL4, p1);
 
-       rt2x00_set_field32(&reg, MAC_CSR13_BIT3, !p2);
-       rt2x00_set_field32(&reg, MAC_CSR13_BIT11, 0);
+       rt2x00_set_field32(&reg, MAC_CSR13_DIR3, 0);
+       rt2x00_set_field32(&reg, MAC_CSR13_VAL3, !p2);
 
        rt2x00pci_register_write(rt2x00dev, MAC_CSR13, reg);
 }
@@ -2855,7 +2855,7 @@ static int rt61pci_probe_hw(struct rt2x00_dev *rt2x00dev)
         * rfkill switch GPIO pin correctly.
         */
        rt2x00pci_register_read(rt2x00dev, MAC_CSR13, &reg);
-       rt2x00_set_field32(&reg, MAC_CSR13_BIT13, 1);
+       rt2x00_set_field32(&reg, MAC_CSR13_DIR5, 1);
        rt2x00pci_register_write(rt2x00dev, MAC_CSR13, reg);
 
        /*
index 9ee0c33175fdf72954af1bb5f8999a41cf058024..9bc6b6044e34189e6a069a4168a7eaec53565a00 100644 (file)
@@ -357,20 +357,22 @@ struct hw_pairwise_ta_entry {
 
 /*
  * MAC_CSR13: GPIO.
+ *     MAC_CSR13_VALx: GPIO value
+ *     MAC_CSR13_DIRx: GPIO direction: 0 = output; 1 = input
  */
 #define MAC_CSR13                      0x3034
-#define MAC_CSR13_BIT0                 FIELD32(0x00000001)
-#define MAC_CSR13_BIT1                 FIELD32(0x00000002)
-#define MAC_CSR13_BIT2                 FIELD32(0x00000004)
-#define MAC_CSR13_BIT3                 FIELD32(0x00000008)
-#define MAC_CSR13_BIT4                 FIELD32(0x00000010)
-#define MAC_CSR13_BIT5                 FIELD32(0x00000020)
-#define MAC_CSR13_BIT8                 FIELD32(0x00000100)
-#define MAC_CSR13_BIT9                 FIELD32(0x00000200)
-#define MAC_CSR13_BIT10                        FIELD32(0x00000400)
-#define MAC_CSR13_BIT11                        FIELD32(0x00000800)
-#define MAC_CSR13_BIT12                        FIELD32(0x00001000)
-#define MAC_CSR13_BIT13                        FIELD32(0x00002000)
+#define MAC_CSR13_VAL0                 FIELD32(0x00000001)
+#define MAC_CSR13_VAL1                 FIELD32(0x00000002)
+#define MAC_CSR13_VAL2                 FIELD32(0x00000004)
+#define MAC_CSR13_VAL3                 FIELD32(0x00000008)
+#define MAC_CSR13_VAL4                 FIELD32(0x00000010)
+#define MAC_CSR13_VAL5                 FIELD32(0x00000020)
+#define MAC_CSR13_DIR0                 FIELD32(0x00000100)
+#define MAC_CSR13_DIR1                 FIELD32(0x00000200)
+#define MAC_CSR13_DIR2                 FIELD32(0x00000400)
+#define MAC_CSR13_DIR3                 FIELD32(0x00000800)
+#define MAC_CSR13_DIR4                 FIELD32(0x00001000)
+#define MAC_CSR13_DIR5                 FIELD32(0x00002000)
 
 /*
  * MAC_CSR14: LED control register.
index 248436c13ce04ae1f79312c6cbb1e16d8a4b5fc9..cfa9f37cccc20917f4b9be9fff67890d9e611287 100644 (file)
@@ -189,7 +189,7 @@ static int rt73usb_rfkill_poll(struct rt2x00_dev *rt2x00dev)
        u32 reg;
 
        rt2x00usb_register_read(rt2x00dev, MAC_CSR13, &reg);
-       return rt2x00_get_field32(reg, MAC_CSR13_BIT7);
+       return rt2x00_get_field32(reg, MAC_CSR13_VAL7);
 }
 
 #ifdef CONFIG_RT2X00_LIB_LEDS
@@ -2195,7 +2195,7 @@ static int rt73usb_probe_hw(struct rt2x00_dev *rt2x00dev)
         * rfkill switch GPIO pin correctly.
         */
        rt2x00usb_register_read(rt2x00dev, MAC_CSR13, &reg);
-       rt2x00_set_field32(&reg, MAC_CSR13_BIT15, 0);
+       rt2x00_set_field32(&reg, MAC_CSR13_DIR7, 0);
        rt2x00usb_register_write(rt2x00dev, MAC_CSR13, reg);
 
        /*
index df1cc116b83be891ee2ff20702260f5949d3d983..7577e0ba3877363cb63480b42c4e118f599de7ef 100644 (file)
@@ -267,24 +267,26 @@ struct hw_pairwise_ta_entry {
 
 /*
  * MAC_CSR13: GPIO.
+ *     MAC_CSR13_VALx: GPIO value
+ *     MAC_CSR13_DIRx: GPIO direction: 0 = input; 1 = output
  */
 #define MAC_CSR13                      0x3034
-#define MAC_CSR13_BIT0                 FIELD32(0x00000001)
-#define MAC_CSR13_BIT1                 FIELD32(0x00000002)
-#define MAC_CSR13_BIT2                 FIELD32(0x00000004)
-#define MAC_CSR13_BIT3                 FIELD32(0x00000008)
-#define MAC_CSR13_BIT4                 FIELD32(0x00000010)
-#define MAC_CSR13_BIT5                 FIELD32(0x00000020)
-#define MAC_CSR13_BIT6                 FIELD32(0x00000040)
-#define MAC_CSR13_BIT7                 FIELD32(0x00000080)
-#define MAC_CSR13_BIT8                 FIELD32(0x00000100)
-#define MAC_CSR13_BIT9                 FIELD32(0x00000200)
-#define MAC_CSR13_BIT10                        FIELD32(0x00000400)
-#define MAC_CSR13_BIT11                        FIELD32(0x00000800)
-#define MAC_CSR13_BIT12                        FIELD32(0x00001000)
-#define MAC_CSR13_BIT13                        FIELD32(0x00002000)
-#define MAC_CSR13_BIT14                        FIELD32(0x00004000)
-#define MAC_CSR13_BIT15                        FIELD32(0x00008000)
+#define MAC_CSR13_VAL0                 FIELD32(0x00000001)
+#define MAC_CSR13_VAL1                 FIELD32(0x00000002)
+#define MAC_CSR13_VAL2                 FIELD32(0x00000004)
+#define MAC_CSR13_VAL3                 FIELD32(0x00000008)
+#define MAC_CSR13_VAL4                 FIELD32(0x00000010)
+#define MAC_CSR13_VAL5                 FIELD32(0x00000020)
+#define MAC_CSR13_VAL6                 FIELD32(0x00000040)
+#define MAC_CSR13_VAL7                 FIELD32(0x00000080)
+#define MAC_CSR13_DIR0                 FIELD32(0x00000100)
+#define MAC_CSR13_DIR1                 FIELD32(0x00000200)
+#define MAC_CSR13_DIR2                 FIELD32(0x00000400)
+#define MAC_CSR13_DIR3                 FIELD32(0x00000800)
+#define MAC_CSR13_DIR4                 FIELD32(0x00001000)
+#define MAC_CSR13_DIR5                 FIELD32(0x00002000)
+#define MAC_CSR13_DIR6                 FIELD32(0x00004000)
+#define MAC_CSR13_DIR7                 FIELD32(0x00008000)
 
 /*
  * MAC_CSR14: LED control register.