drm/amdgpu/gfx11: clean up and consolidate sw_init

With the ME details fixed, we can now consolidate
this state.  Also split out the userq setup into a separate
switch statement so that we can set them per IP version
when the firmwares are ready.

Reviewed-by: Sunil Khatri <sunil.khatri@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
index 23f4d097fa8cb60f664378cfca1de45fd489a93e..29793caa646616230fa5946dd445d6a888dd6e15 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
@@ -1597,14 +1597,35 @@ static int gfx_v11_0_sw_init(struct amdgpu_ip_block *ip_block)
 
        switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
        case IP_VERSION(11, 0, 0):
+       case IP_VERSION(11, 0, 1):
        case IP_VERSION(11, 0, 2):
        case IP_VERSION(11, 0, 3):
+       case IP_VERSION(11, 0, 4):
+       case IP_VERSION(11, 5, 0):
+       case IP_VERSION(11, 5, 1):
+       case IP_VERSION(11, 5, 2):
+       case IP_VERSION(11, 5, 3):
                adev->gfx.me.num_me = 1;
                adev->gfx.me.num_pipe_per_me = 1;
                adev->gfx.me.num_queue_per_pipe = 2;
                adev->gfx.mec.num_mec = 1;
                adev->gfx.mec.num_pipe_per_mec = 4;
                adev->gfx.mec.num_queue_per_pipe = 4;
+               break;
+       default:
+               adev->gfx.me.num_me = 1;
+               adev->gfx.me.num_pipe_per_me = 1;
+               adev->gfx.me.num_queue_per_pipe = 1;
+               adev->gfx.mec.num_mec = 1;
+               adev->gfx.mec.num_pipe_per_mec = 4;
+               adev->gfx.mec.num_queue_per_pipe = 8;
+               break;
+       }
+
+       switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
+       case IP_VERSION(11, 0, 0):
+       case IP_VERSION(11, 0, 2):
+       case IP_VERSION(11, 0, 3):
 #ifdef CONFIG_DRM_AMDGPU_NAVI3X_USERQ
                /* add firmware version checks here */
                if (0) {
@@ -1619,12 +1640,6 @@ static int gfx_v11_0_sw_init(struct amdgpu_ip_block *ip_block)
        case IP_VERSION(11, 5, 1):
        case IP_VERSION(11, 5, 2):
        case IP_VERSION(11, 5, 3):
-               adev->gfx.me.num_me = 1;
-               adev->gfx.me.num_pipe_per_me = 1;
-               adev->gfx.me.num_queue_per_pipe = 2;
-               adev->gfx.mec.num_mec = 1;
-               adev->gfx.mec.num_pipe_per_mec = 4;
-               adev->gfx.mec.num_queue_per_pipe = 4;
 #ifdef CONFIG_DRM_AMDGPU_NAVI3X_USERQ
                /* add firmware version checks here */
                if (0) {
@@ -1634,12 +1649,6 @@ static int gfx_v11_0_sw_init(struct amdgpu_ip_block *ip_block)
 #endif
                break;
        default:
-               adev->gfx.me.num_me = 1;
-               adev->gfx.me.num_pipe_per_me = 1;
-               adev->gfx.me.num_queue_per_pipe = 1;
-               adev->gfx.mec.num_mec = 1;
-               adev->gfx.mec.num_pipe_per_mec = 4;
-               adev->gfx.mec.num_queue_per_pipe = 8;
                break;
        }