TC_PORT_LEGACY,
};
-enum dpio_channel {
- DPIO_CH0,
- DPIO_CH1
-};
-
-enum dpio_phy {
- DPIO_PHY0,
- DPIO_PHY1,
- DPIO_PHY2,
-};
-
enum aux_ch {
AUX_CH_A,
AUX_CH_B,
#include <linux/types.h>
-#include "intel_display.h"
#include "intel_display_power.h"
+#include "intel_dpio_phy.h"
struct drm_i915_private;
struct i915_power_well;
#include <linux/types.h>
-enum dpio_channel;
-enum dpio_phy;
enum pipe;
enum port;
struct drm_i915_private;
struct intel_digital_port;
struct intel_encoder;
+enum dpio_channel {
+ DPIO_CH0,
+ DPIO_CH1,
+};
+
+enum dpio_phy {
+ DPIO_PHY0,
+ DPIO_PHY1,
+ DPIO_PHY2,
+};
+
void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port,
enum dpio_phy *phy, enum dpio_channel *ch);
void bxt_ddi_phy_set_signal_levels(struct intel_encoder *encoder,
#include "i915_reg.h"
#include "gvt.h"
+#include "display/intel_dpio_phy.h"
+
static int get_edp_pipe(struct intel_vgpu *vgpu)
{
u32 data = vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP);
#include "intel_mchbar_regs.h"
#include "display/intel_display_types.h"
#include "display/intel_dmc_regs.h"
+#include "display/intel_dpio_phy.h"
#include "display/intel_fbc.h"
#include "display/vlv_dsi_pll_regs.h"
#include "gt/intel_gt_regs.h"
#include "i915_reg.h"
#include "gvt.h"
+#include "display/intel_dpio_phy.h"
#include "gt/intel_gt_regs.h"
/**
#include "display/intel_audio_regs.h"
#include "display/intel_backlight_regs.h"
#include "display/intel_dmc_regs.h"
+#include "display/intel_dpio_phy.h"
#include "display/vlv_dsi_pll_regs.h"
#include "gt/intel_gt_regs.h"
#include "gvt/gvt.h"
#include "i915_reg.h"
#include "vlv_sideband.h"
+#include "display/intel_dpio_phy.h"
+
/*
* IOSF sideband, see VLV2_SidebandMsg_HAS.docx and
* VLV_VLV2_PUNIT_HAS_0.8.docx