arm64: dts: ti: k3-j721s2: Add support for CAN instances 3 and 5 in main domain

CAN instances 3 and 5 in the main domain are brought on the common
processor board through header J27 and J28. The CAN High and Low lines
from the SoC are routed through a mux on the SoM. The select lines need
to be set for the CAN signals to get connected to the transceivers on
the common processor board. Threfore, add respective mux, transceiver
dt nodes to add support for these CAN instances.

Reviewed-by: Udit Kumar <u-kumar1@ti.com>
Signed-off-by: Bhavya Kapoor <b-kapoor@ti.com>
Link: https://lore.kernel.org/r/20230725085939.536766-1-b-kapoor@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>

diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
index 02b7a559bdf218dd420755788668fd0408ca53ac..20b32563c0ed559c8ed96a69fd149f7f5a4a6472 100644 (file)
--- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
@@ -30,6 +30,8 @@
                can0 = &main_mcan16;
                can1 = &mcu_mcan0;
                can2 = &mcu_mcan1;
+               can3 = &main_mcan3;
+               can4 = &main_mcan5;
        };
 
        evm_12v0: fixedregulator-evm12v0 {
@@ -110,6 +112,22 @@
                standby-gpios = <&wkup_gpio0 2 GPIO_ACTIVE_HIGH>;
        };
 
+       transceiver3: can-phy3 {
+               compatible = "ti,tcan1043";
+               #phy-cells = <0>;
+               max-bitrate = <5000000>;
+               standby-gpios = <&exp2 7 GPIO_ACTIVE_LOW>;
+               enable-gpios = <&exp2 6 GPIO_ACTIVE_HIGH>;
+               mux-states = <&mux0 1>;
+       };
+
+       transceiver4: can-phy4 {
+               compatible = "ti,tcan1042";
+               #phy-cells = <0>;
+               max-bitrate = <5000000>;
+               standby-gpios = <&exp_som 7 GPIO_ACTIVE_HIGH>;
+               mux-states = <&mux1 1>;
+       };
 };
 
 &main_pmx0 {
@@ -153,6 +171,20 @@
                        J721S2_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AG25) TIMER_IO1.USB0_DRVVBUS */
                >;
        };
+
+       main_mcan3_pins_default: main-mcan3-default-pins {
+               pinctrl-single,pins = <
+                       J721S2_IOPAD(0x080, PIN_INPUT, 0) /* (U26) MCASP0_AXR4.MCAN3_RX */
+                       J721S2_IOPAD(0x07c, PIN_OUTPUT, 0) /* (T27) MCASP0_AXR3.MCAN3_TX */
+               >;
+       };
+
+       main_mcan5_pins_default: main-mcan5-default-pins {
+               pinctrl-single,pins = <
+                       J721S2_IOPAD(0x03c, PIN_INPUT, 0) /* (U27) MCASP0_AFSX.MCAN5_RX */
+                       J721S2_IOPAD(0x038, PIN_OUTPUT, 0) /* (AB28) MCASP0_ACLKX.MCAN5_TX */
+               >;
+       };
 };
 
 &wkup_pmx2 {
@@ -461,3 +493,17 @@
                ti,adc-channels = <0 1 2 3 4 5 6 7>;
        };
 };
+
+&main_mcan3 {
+       status = "okay";
+       pinctrl-names = "default";
+       pinctrl-0 = <&main_mcan3_pins_default>;
+       phys = <&transceiver3>;
+};
+
+&main_mcan5 {
+       status = "okay";
+       pinctrl-names = "default";
+       pinctrl-0 = <&main_mcan5_pins_default>;
+       phys = <&transceiver4>;
+};

diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi
index d57dd43da0ef4141c4b412337b6c4fc3fe59534b..5947664820712446fc61eb5e4425afa73f30e89d 100644 (file)
--- a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi
@@ -31,6 +31,18 @@
                };
        };
 
+       mux0: mux-controller {
+               compatible = "gpio-mux";
+               #mux-state-cells = <1>;
+               mux-gpios = <&exp_som 1 GPIO_ACTIVE_HIGH>;
+       };
+
+       mux1: mux-controller {
+               compatible = "gpio-mux";
+               #mux-state-cells = <1>;
+               mux-gpios = <&exp_som 2 GPIO_ACTIVE_HIGH>;
+       };
+
        transceiver0: can-phy0 {
                /* standby pin has been grounded by default */
                compatible = "ti,tcan1042";