arm64: dts: renesas: r9a09g047: Add pincontrol node

Add pincontrol node to RZ/G3E ("R9A09G047") SoC DTSI.

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/20241216195325.164212-7-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
index 7a422e9ad29e9fe125607f3ac470900459b79e1e..200e9ea8919354baf2179324f351b644aab77c70 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
@@ -131,6 +131,19 @@
                #size-cells = <2>;
                ranges;
 
+               pinctrl: pinctrl@10410000 {
+                       compatible = "renesas,r9a09g047-pinctrl";
+                       reg = <0 0x10410000 0 0x10000>;
+                       clocks = <&cpg CPG_CORE R9A09G047_IOTOP_0_SHCLK>;
+                       gpio-controller;
+                       #gpio-cells = <2>;
+                       gpio-ranges = <&pinctrl 0 0 232>;
+                       #interrupt-cells = <2>;
+                       interrupt-controller;
+                       power-domains = <&cpg>;
+                       resets = <&cpg 0xa5>, <&cpg 0xa6>;
+               };
+
                cpg: clock-controller@10420000 {
                        compatible = "renesas,r9a09g047-cpg";
                        reg = <0 0x10420000 0 0x10000>;