drm/i915/xe2hpd: Add new C20 PHY SRAM address

Xe2_HPD has different offsets for C20 PHY SRAM configuration context
location. Use the display version to select the right address.

Note that Xe2_LPD uses the same C20 SRAM offsets used by Xe_LPDP (i.e.
MTL's display). According to the BSpec, currently, only Xe2_HPD has
different offsets, so make sure it is the only display using them in the
driver.

v2:
* Redesigned how the right offsets are selected for different display
IP versions.
v3: Fix white space error(RK)

Bspec: 67610
Cc: Clint Taylor <Clinton.A.Taylor@intel.com>
Cc: Gustavo Sousa <gustavo.sousa@intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Reviewed-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240430172850.1881525-7-radhakrishna.sripada@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 8621f71e15b4ea8076361dc313965c8037b3abab..98588bba7f491d3e3877297f875881efa8232aa4 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -2161,6 +2161,7 @@ static void intel_c20pll_readout_hw_state(struct intel_encoder *encoder,
        bool cntx;
        intel_wakeref_t wakeref;
        int i;
+       struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 
        wakeref = intel_cx0_phy_transaction_begin(encoder);
 
@@ -2170,42 +2171,50 @@ static void intel_c20pll_readout_hw_state(struct intel_encoder *encoder,
        /* Read Tx configuration */
        for (i = 0; i < ARRAY_SIZE(pll_state->tx); i++) {
                if (cntx)
-                       pll_state->tx[i] = intel_c20_sram_read(encoder, INTEL_CX0_LANE0,
-                                                              PHY_C20_B_TX_CNTX_CFG(i));
+                       pll_state->tx[i] = intel_c20_sram_read(encoder,
+                                                              INTEL_CX0_LANE0,
+                                                              PHY_C20_B_TX_CNTX_CFG(i915, i));
                else
-                       pll_state->tx[i] = intel_c20_sram_read(encoder, INTEL_CX0_LANE0,
-                                                              PHY_C20_A_TX_CNTX_CFG(i));
+                       pll_state->tx[i] = intel_c20_sram_read(encoder,
+                                                              INTEL_CX0_LANE0,
+                                                              PHY_C20_A_TX_CNTX_CFG(i915, i));
        }
 
        /* Read common configuration */
        for (i = 0; i < ARRAY_SIZE(pll_state->cmn); i++) {
                if (cntx)
-                       pll_state->cmn[i] = intel_c20_sram_read(encoder, INTEL_CX0_LANE0,
-                                                               PHY_C20_B_CMN_CNTX_CFG(i));
+                       pll_state->cmn[i] = intel_c20_sram_read(encoder,
+                                                               INTEL_CX0_LANE0,
+                                                               PHY_C20_B_CMN_CNTX_CFG(i915, i));
                else
-                       pll_state->cmn[i] = intel_c20_sram_read(encoder, INTEL_CX0_LANE0,
-                                                               PHY_C20_A_CMN_CNTX_CFG(i));
+                       pll_state->cmn[i] = intel_c20_sram_read(encoder,
+                                                               INTEL_CX0_LANE0,
+                                                               PHY_C20_A_CMN_CNTX_CFG(i915, i));
        }
 
        if (intel_c20phy_use_mpllb(pll_state)) {
                /* MPLLB configuration */
                for (i = 0; i < ARRAY_SIZE(pll_state->mpllb); i++) {
                        if (cntx)
-                               pll_state->mpllb[i] = intel_c20_sram_read(encoder, INTEL_CX0_LANE0,
-                                                                         PHY_C20_B_MPLLB_CNTX_CFG(i));
+                               pll_state->mpllb[i] = intel_c20_sram_read(encoder,
+                                                                         INTEL_CX0_LANE0,
+                                                                         PHY_C20_B_MPLLB_CNTX_CFG(i915, i));
                        else
-                               pll_state->mpllb[i] = intel_c20_sram_read(encoder, INTEL_CX0_LANE0,
-                                                                         PHY_C20_A_MPLLB_CNTX_CFG(i));
+                               pll_state->mpllb[i] = intel_c20_sram_read(encoder,
+                                                                         INTEL_CX0_LANE0,
+                                                                         PHY_C20_A_MPLLB_CNTX_CFG(i915, i));
                }
        } else {
                /* MPLLA configuration */
                for (i = 0; i < ARRAY_SIZE(pll_state->mplla); i++) {
                        if (cntx)
-                               pll_state->mplla[i] = intel_c20_sram_read(encoder, INTEL_CX0_LANE0,
-                                                                         PHY_C20_B_MPLLA_CNTX_CFG(i));
+                               pll_state->mplla[i] = intel_c20_sram_read(encoder,
+                                                                         INTEL_CX0_LANE0,
+                                                                         PHY_C20_B_MPLLA_CNTX_CFG(i915, i));
                        else
-                               pll_state->mplla[i] = intel_c20_sram_read(encoder, INTEL_CX0_LANE0,
-                                                                         PHY_C20_A_MPLLA_CNTX_CFG(i));
+                               pll_state->mplla[i] = intel_c20_sram_read(encoder,
+                                                                         INTEL_CX0_LANE0,
+                                                                         PHY_C20_A_MPLLA_CNTX_CFG(i915, i));
                }
        }
 
@@ -2363,17 +2372,25 @@ static void intel_c20_pll_program(struct drm_i915_private *i915,
        /* 3.1 Tx configuration */
        for (i = 0; i < ARRAY_SIZE(pll_state->tx); i++) {
                if (cntx)
-                       intel_c20_sram_write(encoder, INTEL_CX0_LANE0, PHY_C20_A_TX_CNTX_CFG(i), pll_state->tx[i]);
+                       intel_c20_sram_write(encoder, INTEL_CX0_LANE0,
+                                            PHY_C20_A_TX_CNTX_CFG(i915, i),
+                                            pll_state->tx[i]);
                else
-                       intel_c20_sram_write(encoder, INTEL_CX0_LANE0, PHY_C20_B_TX_CNTX_CFG(i), pll_state->tx[i]);
+                       intel_c20_sram_write(encoder, INTEL_CX0_LANE0,
+                                            PHY_C20_B_TX_CNTX_CFG(i915, i),
+                                            pll_state->tx[i]);
        }
 
        /* 3.2 common configuration */
        for (i = 0; i < ARRAY_SIZE(pll_state->cmn); i++) {
                if (cntx)
-                       intel_c20_sram_write(encoder, INTEL_CX0_LANE0, PHY_C20_A_CMN_CNTX_CFG(i), pll_state->cmn[i]);
+                       intel_c20_sram_write(encoder, INTEL_CX0_LANE0,
+                                            PHY_C20_A_CMN_CNTX_CFG(i915, i),
+                                            pll_state->cmn[i]);
                else
-                       intel_c20_sram_write(encoder, INTEL_CX0_LANE0, PHY_C20_B_CMN_CNTX_CFG(i), pll_state->cmn[i]);
+                       intel_c20_sram_write(encoder, INTEL_CX0_LANE0,
+                                            PHY_C20_B_CMN_CNTX_CFG(i915, i),
+                                            pll_state->cmn[i]);
        }
 
        /* 3.3 mpllb or mplla configuration */
@@ -2381,22 +2398,22 @@ static void intel_c20_pll_program(struct drm_i915_private *i915,
                for (i = 0; i < ARRAY_SIZE(pll_state->mpllb); i++) {
                        if (cntx)
                                intel_c20_sram_write(encoder, INTEL_CX0_LANE0,
-                                                    PHY_C20_A_MPLLB_CNTX_CFG(i),
+                                                    PHY_C20_A_MPLLB_CNTX_CFG(i915, i),
                                                     pll_state->mpllb[i]);
                        else
                                intel_c20_sram_write(encoder, INTEL_CX0_LANE0,
-                                                    PHY_C20_B_MPLLB_CNTX_CFG(i),
+                                                    PHY_C20_B_MPLLB_CNTX_CFG(i915, i),
                                                     pll_state->mpllb[i]);
                }
        } else {
                for (i = 0; i < ARRAY_SIZE(pll_state->mplla); i++) {
                        if (cntx)
                                intel_c20_sram_write(encoder, INTEL_CX0_LANE0,
-                                                    PHY_C20_A_MPLLA_CNTX_CFG(i),
+                                                    PHY_C20_A_MPLLA_CNTX_CFG(i915, i),
                                                     pll_state->mplla[i]);
                        else
                                intel_c20_sram_write(encoder, INTEL_CX0_LANE0,
-                                                    PHY_C20_B_MPLLA_CNTX_CFG(i),
+                                                    PHY_C20_B_MPLLA_CNTX_CFG(i915, i),
                                                     pll_state->mplla[i]);
                }
        }

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
index bdd0c8c4ef9743d558f295faf81ea6b2dbaef61c..ab3ae110b68f3f149e695b9b470c2d7005ffa3d2 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
@@ -254,18 +254,50 @@
 #define PHY_C20_VDR_CUSTOM_WIDTH       0xD02
 #define   PHY_C20_CUSTOM_WIDTH_MASK    REG_GENMASK(1, 0)
 #define   PHY_C20_CUSTOM_WIDTH(val)    REG_FIELD_PREP8(PHY_C20_CUSTOM_WIDTH_MASK, val)
-#define PHY_C20_A_TX_CNTX_CFG(idx)     (0xCF2E - (idx))
-#define PHY_C20_B_TX_CNTX_CFG(idx)     (0xCF2A - (idx))
+
+#define _MTL_C20_A_TX_CNTX_CFG 0xCF2E
+#define _MTL_C20_B_TX_CNTX_CFG 0xCF2A
+#define _MTL_C20_A_CMN_CNTX_CFG        0xCDAA
+#define _MTL_C20_B_CMN_CNTX_CFG        0xCDA5
+#define _MTL_C20_A_MPLLA_CFG   0xCCF0
+#define _MTL_C20_B_MPLLA_CFG   0xCCE5
+#define _MTL_C20_A_MPLLB_CFG   0xCB5A
+#define _MTL_C20_B_MPLLB_CFG   0xCB4E
+
+#define _XE2HPD_C20_A_TX_CNTX_CFG      0xCF5E
+#define _XE2HPD_C20_B_TX_CNTX_CFG      0xCF5A
+#define _XE2HPD_C20_A_CMN_CNTX_CFG     0xCE8E
+#define _XE2HPD_C20_B_CMN_CNTX_CFG     0xCE89
+#define _XE2HPD_C20_A_MPLLA_CFG                0xCE58
+#define _XE2HPD_C20_B_MPLLA_CFG                0xCE4D
+#define _XE2HPD_C20_A_MPLLB_CFG                0xCCC2
+#define _XE2HPD_C20_B_MPLLB_CFG                0xCCB6
+
+#define _IS_XE2HPD_C20(i915)   (DISPLAY_VER_FULL(i915) == IP_VER(14, 1))
+
+#define PHY_C20_A_TX_CNTX_CFG(i915, idx) \
+               ((_IS_XE2HPD_C20(i915) ? _XE2HPD_C20_A_TX_CNTX_CFG : _MTL_C20_A_TX_CNTX_CFG) - (idx))
+#define PHY_C20_B_TX_CNTX_CFG(i915, idx) \
+               ((_IS_XE2HPD_C20(i915) ? _XE2HPD_C20_B_TX_CNTX_CFG : _MTL_C20_B_TX_CNTX_CFG) - (idx))
 #define   C20_PHY_TX_RATE              REG_GENMASK(2, 0)
-#define PHY_C20_A_CMN_CNTX_CFG(idx)    (0xCDAA - (idx))
-#define PHY_C20_B_CMN_CNTX_CFG(idx)    (0xCDA5 - (idx))
-#define PHY_C20_A_MPLLA_CNTX_CFG(idx)  (0xCCF0 - (idx))
-#define PHY_C20_B_MPLLA_CNTX_CFG(idx)  (0xCCE5 - (idx))
+
+#define PHY_C20_A_CMN_CNTX_CFG(i915, idx) \
+               ((_IS_XE2HPD_C20(i915) ? _XE2HPD_C20_A_CMN_CNTX_CFG : _MTL_C20_A_CMN_CNTX_CFG) - (idx))
+#define PHY_C20_B_CMN_CNTX_CFG(i915, idx) \
+               ((_IS_XE2HPD_C20(i915) ? _XE2HPD_C20_B_CMN_CNTX_CFG : _MTL_C20_B_CMN_CNTX_CFG) - (idx))
+#define PHY_C20_A_MPLLA_CNTX_CFG(i915, idx) \
+               ((_IS_XE2HPD_C20(i915) ? _XE2HPD_C20_A_MPLLA_CFG : _MTL_C20_A_MPLLA_CFG) - (idx))
+#define PHY_C20_B_MPLLA_CNTX_CFG(i915, idx) \
+               ((_IS_XE2HPD_C20(i915) ? _XE2HPD_C20_B_MPLLA_CFG : _MTL_C20_B_MPLLA_CFG) - (idx))
 #define   C20_MPLLA_FRACEN             REG_BIT(14)
 #define   C20_FB_CLK_DIV4_EN           REG_BIT(13)
 #define   C20_MPLLA_TX_CLK_DIV_MASK    REG_GENMASK(10, 8)
-#define PHY_C20_A_MPLLB_CNTX_CFG(idx)  (0xCB5A - (idx))
-#define PHY_C20_B_MPLLB_CNTX_CFG(idx)  (0xCB4E - (idx))
+
+#define PHY_C20_A_MPLLB_CNTX_CFG(i915, idx) \
+               ((_IS_XE2HPD_C20(i915) ? _XE2HPD_C20_A_MPLLB_CFG : _MTL_C20_A_MPLLB_CFG) - (idx))
+#define PHY_C20_B_MPLLB_CNTX_CFG(i915, idx) \
+               ((_IS_XE2HPD_C20(i915) ? _XE2HPD_C20_B_MPLLB_CFG : _MTL_C20_B_MPLLB_CFG) - (idx))
+
 #define   C20_MPLLB_TX_CLK_DIV_MASK    REG_GENMASK(15, 13)
 #define   C20_MPLLB_FRACEN             REG_BIT(13)
 #define   C20_REF_CLK_MPLLB_DIV_MASK   REG_GENMASK(12, 10)