arm64: Move post_ttbr_update_workaround to C code

We will soon need to invoke a CPU-specific function pointer after changing
page tables, so move post_ttbr_update_workaround out into C code to make
this possible.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/assembler.h
index 215a49213507dd79e4e8683770d98d7dcd49f685..a6f90b648655777f41239392522402274fd37b9c 100644 (file)
--- a/arch/arm64/include/asm/assembler.h
+++ b/arch/arm64/include/asm/assembler.h
@@ -492,19 +492,6 @@ alternative_endif
        mrs     \rd, sp_el0
        .endm
 
-/*
- * Errata workaround post TTBRx_EL1 update.
- */
-       .macro  post_ttbr_update_workaround
-#ifdef CONFIG_CAVIUM_ERRATUM_27456
-alternative_if ARM64_WORKAROUND_CAVIUM_27456
-       ic      iallu
-       dsb     nsh
-       isb
-alternative_else_nop_endif
-#endif
-       .endm
-
 /*
  * Arrange a physical address in a TTBR register, taking care of 52-bit
  * addresses.

diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S
index 6ceed4877daf9307516b45ecc093a1cfcecc271b..80b539845da6f8887074a22301435a7dac59e4ca 100644 (file)
--- a/arch/arm64/kernel/entry.S
+++ b/arch/arm64/kernel/entry.S
@@ -277,7 +277,7 @@ alternative_else_nop_endif
         * Cavium erratum 27456 (broadcast TLBI instructions may cause I-cache
         * corruption).
         */
-       post_ttbr_update_workaround
+       bl      post_ttbr_update_workaround
        .endif
 1:
        .if     \el != 0

diff --git a/arch/arm64/mm/context.c b/arch/arm64/mm/context.c
index 1fe71b9fcf3510cdb9143d96106a7a1faf13941b..511bd1e79b69ca50deca44859c18484bdc555e1f 100644 (file)
--- a/arch/arm64/mm/context.c
+++ b/arch/arm64/mm/context.c
@@ -242,6 +242,15 @@ switch_mm_fastpath:
                cpu_switch_mm(mm->pgd, mm);
 }
 
+/* Errata workaround post TTBRx_EL1 update. */
+asmlinkage void post_ttbr_update_workaround(void)
+{
+       asm(ALTERNATIVE("nop; nop; nop",
+                       "ic iallu; dsb nsh; isb",
+                       ARM64_WORKAROUND_CAVIUM_27456,
+                       CONFIG_CAVIUM_ERRATUM_27456));
+}
+
 static int asids_init(void)
 {
        asid_bits = get_cpu_asid_bits();

diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S
index bc334588f23457b1e9d42d70392110dd60be9dcd..bc86f7ef86204197ca7f70d3e6a6606b1ef3048e 100644 (file)
--- a/arch/arm64/mm/proc.S
+++ b/arch/arm64/mm/proc.S
@@ -146,8 +146,7 @@ ENTRY(cpu_do_switch_mm)
        phys_to_ttbr x0, x2
        msr     ttbr0_el1, x2                   // now update TTBR0
        isb
-       post_ttbr_update_workaround
-       ret
+       b       post_ttbr_update_workaround     // Back to C code...
 ENDPROC(cpu_do_switch_mm)
 
        .pushsection ".idmap.text", "ax"