pinctrl: lynxpoint: Simplify code with cleanup helpers

Use macros defined in linux/cleanup.h to automate resource lifetime
control in the driver.

Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>

diff --git a/drivers/pinctrl/intel/pinctrl-lynxpoint.c b/drivers/pinctrl/intel/pinctrl-lynxpoint.c
index e6878e4cf20cb508d46ae51f74f4403ad3fee105..1fb0bba8b386b9114f240e2767f13888f24821ae 100644 (file)
--- a/drivers/pinctrl/intel/pinctrl-lynxpoint.c
+++ b/drivers/pinctrl/intel/pinctrl-lynxpoint.c
@@ -10,6 +10,7 @@
 #include <linux/acpi.h>
 #include <linux/array_size.h>
 #include <linux/bitops.h>
+#include <linux/cleanup.h>
 #include <linux/gpio/driver.h>
 #include <linux/interrupt.h>
 #include <linux/io.h>
@@ -291,10 +292,9 @@ static int lp_pinmux_set_mux(struct pinctrl_dev *pctldev,
 {
        struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev);
        const struct intel_pingroup *grp = &lg->soc->groups[group];
-       unsigned long flags;
        int i;
 
-       raw_spin_lock_irqsave(&lg->lock, flags);
+       guard(raw_spinlock_irqsave)(&lg->lock);
 
        /* Now enable the mux setting for each pin in the group */
        for (i = 0; i < grp->grp.npins; i++) {
@@ -312,8 +312,6 @@ static int lp_pinmux_set_mux(struct pinctrl_dev *pctldev,
                iowrite32(value, reg);
        }
 
-       raw_spin_unlock_irqrestore(&lg->lock, flags);
-
        return 0;
 }
 
@@ -334,10 +332,9 @@ static int lp_gpio_request_enable(struct pinctrl_dev *pctldev,
        struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev);
        void __iomem *reg = lp_gpio_reg(&lg->chip, pin, LP_CONFIG1);
        void __iomem *conf2 = lp_gpio_reg(&lg->chip, pin, LP_CONFIG2);
-       unsigned long flags;
        u32 value;
 
-       raw_spin_lock_irqsave(&lg->lock, flags);
+       guard(raw_spinlock_irqsave)(&lg->lock);
 
        /*
         * Reconfigure pin to GPIO mode if needed and issue a warning,
@@ -352,8 +349,6 @@ static int lp_gpio_request_enable(struct pinctrl_dev *pctldev,
        /* Enable input sensing */
        lp_gpio_enable_input(conf2);
 
-       raw_spin_unlock_irqrestore(&lg->lock, flags);
-
        return 0;
 }
 
@@ -363,14 +358,11 @@ static void lp_gpio_disable_free(struct pinctrl_dev *pctldev,
 {
        struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev);
        void __iomem *conf2 = lp_gpio_reg(&lg->chip, pin, LP_CONFIG2);
-       unsigned long flags;
 
-       raw_spin_lock_irqsave(&lg->lock, flags);
+       guard(raw_spinlock_irqsave)(&lg->lock);
 
        /* Disable input sensing */
        lp_gpio_disable_input(conf2);
-
-       raw_spin_unlock_irqrestore(&lg->lock, flags);
 }
 
 static int lp_gpio_set_direction(struct pinctrl_dev *pctldev,
@@ -379,10 +371,9 @@ static int lp_gpio_set_direction(struct pinctrl_dev *pctldev,
 {
        struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev);
        void __iomem *reg = lp_gpio_reg(&lg->chip, pin, LP_CONFIG1);
-       unsigned long flags;
        u32 value;
 
-       raw_spin_lock_irqsave(&lg->lock, flags);
+       guard(raw_spinlock_irqsave)(&lg->lock);
 
        value = ioread32(reg);
        value &= ~DIR_BIT;
@@ -400,8 +391,6 @@ static int lp_gpio_set_direction(struct pinctrl_dev *pctldev,
        }
        iowrite32(value, reg);
 
-       raw_spin_unlock_irqrestore(&lg->lock, flags);
-
        return 0;
 }
 
@@ -421,13 +410,11 @@ static int lp_pin_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
        struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev);
        void __iomem *conf2 = lp_gpio_reg(&lg->chip, pin, LP_CONFIG2);
        enum pin_config_param param = pinconf_to_config_param(*config);
-       unsigned long flags;
        u32 value, pull;
        u16 arg;
 
-       raw_spin_lock_irqsave(&lg->lock, flags);
-       value = ioread32(conf2);
-       raw_spin_unlock_irqrestore(&lg->lock, flags);
+       scoped_guard(raw_spinlock_irqsave, &lg->lock)
+               value = ioread32(conf2);
 
        pull = value & GPIWP_MASK;
 
@@ -464,11 +451,10 @@ static int lp_pin_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
        struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev);
        void __iomem *conf2 = lp_gpio_reg(&lg->chip, pin, LP_CONFIG2);
        enum pin_config_param param;
-       unsigned long flags;
-       int i, ret = 0;
+       unsigned int i;
        u32 value;
 
-       raw_spin_lock_irqsave(&lg->lock, flags);
+       guard(raw_spinlock_irqsave)(&lg->lock);
 
        value = ioread32(conf2);
 
@@ -489,19 +475,13 @@ static int lp_pin_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
                        value |= GPIWP_UP;
                        break;
                default:
-                       ret = -ENOTSUPP;
+                       return -ENOTSUPP;
                }
-
-               if (ret)
-                       break;
        }
 
-       if (!ret)
-               iowrite32(value, conf2);
+       iowrite32(value, conf2);
 
-       raw_spin_unlock_irqrestore(&lg->lock, flags);
-
-       return ret;
+       return 0;
 }
 
 static const struct pinconf_ops lptlp_pinconf_ops = {
@@ -527,16 +507,13 @@ static void lp_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
 {
        struct intel_pinctrl *lg = gpiochip_get_data(chip);
        void __iomem *reg = lp_gpio_reg(chip, offset, LP_CONFIG1);
-       unsigned long flags;
 
-       raw_spin_lock_irqsave(&lg->lock, flags);
+       guard(raw_spinlock_irqsave)(&lg->lock);
 
        if (value)
                iowrite32(ioread32(reg) | OUT_LVL_BIT, reg);
        else
                iowrite32(ioread32(reg) & ~OUT_LVL_BIT, reg);
-
-       raw_spin_unlock_irqrestore(&lg->lock, flags);
 }
 
 static int lp_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
@@ -592,11 +569,10 @@ static void lp_irq_ack(struct irq_data *d)
        struct intel_pinctrl *lg = gpiochip_get_data(gc);
        irq_hw_number_t hwirq = irqd_to_hwirq(d);
        void __iomem *reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_STAT);
-       unsigned long flags;
 
-       raw_spin_lock_irqsave(&lg->lock, flags);
+       guard(raw_spinlock_irqsave)(&lg->lock);
+
        iowrite32(BIT(hwirq % 32), reg);
-       raw_spin_unlock_irqrestore(&lg->lock, flags);
 }
 
 static void lp_irq_unmask(struct irq_data *d)
@@ -613,13 +589,11 @@ static void lp_irq_enable(struct irq_data *d)
        struct intel_pinctrl *lg = gpiochip_get_data(gc);
        irq_hw_number_t hwirq = irqd_to_hwirq(d);
        void __iomem *reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_ENABLE);
-       unsigned long flags;
 
        gpiochip_enable_irq(gc, hwirq);
 
-       raw_spin_lock_irqsave(&lg->lock, flags);
-       iowrite32(ioread32(reg) | BIT(hwirq % 32), reg);
-       raw_spin_unlock_irqrestore(&lg->lock, flags);
+       scoped_guard(raw_spinlock_irqsave, &lg->lock)
+               iowrite32(ioread32(reg) | BIT(hwirq % 32), reg);
 }
 
 static void lp_irq_disable(struct irq_data *d)
@@ -628,11 +602,9 @@ static void lp_irq_disable(struct irq_data *d)
        struct intel_pinctrl *lg = gpiochip_get_data(gc);
        irq_hw_number_t hwirq = irqd_to_hwirq(d);
        void __iomem *reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_ENABLE);
-       unsigned long flags;
 
-       raw_spin_lock_irqsave(&lg->lock, flags);
-       iowrite32(ioread32(reg) & ~BIT(hwirq % 32), reg);
-       raw_spin_unlock_irqrestore(&lg->lock, flags);
+       scoped_guard(raw_spinlock_irqsave, &lg->lock)
+               iowrite32(ioread32(reg) & ~BIT(hwirq % 32), reg);
 
        gpiochip_disable_irq(gc, hwirq);
 }
@@ -642,7 +614,6 @@ static int lp_irq_set_type(struct irq_data *d, unsigned int type)
        struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
        struct intel_pinctrl *lg = gpiochip_get_data(gc);
        irq_hw_number_t hwirq = irqd_to_hwirq(d);
-       unsigned long flags;
        void __iomem *reg;
        u32 value;
 
@@ -656,7 +627,8 @@ static int lp_irq_set_type(struct irq_data *d, unsigned int type)
                return -EBUSY;
        }
 
-       raw_spin_lock_irqsave(&lg->lock, flags);
+       guard(raw_spinlock_irqsave)(&lg->lock);
+
        value = ioread32(reg);
 
        /* set both TRIG_SEL and INV bits to 0 for rising edge */
@@ -682,8 +654,6 @@ static int lp_irq_set_type(struct irq_data *d, unsigned int type)
        else if (type & IRQ_TYPE_LEVEL_MASK)
                irq_set_handler_locked(d, handle_level_irq);
 
-       raw_spin_unlock_irqrestore(&lg->lock, flags);
-
        return 0;
 }