parisc: Fix itlb miss handler for 64-bit programs

For an itlb miss when executing code above 4 Gb on ILP64 adjust the
iasq/iaoq in the same way isr/ior was adjusted.  This fixes signal
delivery for the 64-bit static test program from
http://ftp.parisc-linux.org/src/64bit.tar.gz.  Note that signals are
handled by the signal trampoline code in the 64-bit VDSO which is mapped
into high userspace memory region above 4GB for 64-bit processes.

Signed-off-by: Helge Deller <deller@gmx.de>
Cc: stable@vger.kernel.org	# v4.19+

diff --git a/arch/parisc/kernel/entry.S b/arch/parisc/kernel/entry.S
index ab23e61a6f016a5ff69cb340588a0a446aada880..ea57bcc21dc5fe31f045ffcee6a6ba0420c6cd30 100644 (file)
--- a/arch/parisc/kernel/entry.S
+++ b/arch/parisc/kernel/entry.S
@@ -1051,8 +1051,7 @@ ENTRY_CFI(intr_save)              /* for os_hpmc */
        STREG           %r16, PT_ISR(%r29)
        STREG           %r17, PT_IOR(%r29)
 
-#if 0 && defined(CONFIG_64BIT)
-       /* Revisit when we have 64-bit code above 4Gb */
+#if defined(CONFIG_64BIT)
        b,n             intr_save2
 
 skip_save_ior:
@@ -1060,8 +1059,7 @@ skip_save_ior:
         * need to adjust iasq/iaoq here in the same way we adjusted isr/ior
         * above.
         */
-       extrd,u,*       %r8,PSW_W_BIT,1,%r1
-       cmpib,COND(=),n 1,%r1,intr_save2
+       bb,COND(>=),n   %r8,PSW_W_BIT,intr_save2
        LDREG           PT_IASQ0(%r29), %r16
        LDREG           PT_IAOQ0(%r29), %r17
        /* adjust iasq/iaoq */