drm/amd/display: Block Invalid TMDS operation
authorChris Park <chris.park@amd.com>
Tue, 3 Dec 2024 19:33:16 +0000 (14:33 -0500)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 18 Dec 2024 17:21:37 +0000 (12:21 -0500)
[Why]
When sink type is TMDS, PHY programming does not block against pixel
clock greater than 600MHz.

[How]
Based on sink type, block greater than 600MHz phy programming.

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: Aric Cyr <aric.cyr@amd.com>
Signed-off-by: Chris Park <chris.park@amd.com>
Signed-off-by: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
drivers/gpu/drm/amd/display/dc/link/link_dpms.c

index b700608e4240302be2a49d458c5099acac3b52be..077337698e0adcacedb5e1d702e0d79f45995b94 100644 (file)
@@ -1105,6 +1105,9 @@ static bool dcn401_program_pix_clk(
                                &dto_params);
 
        } else {
+               if (pll_settings->actual_pix_clk_100hz > 6000000UL)
+                       return false;
+
                /* disables DP DTO when provided with TMDS signal type */
                clock_source->ctx->dc->res_pool->dccg->funcs->set_dp_dto(
                                clock_source->ctx->dc->res_pool->dccg,
index 5d66bfc7fe6e6d4a488a5434682a2b358508cee5..60e64e0138a32e9a6281b6c2c57a66f68a6df2a1 100644 (file)
@@ -1953,6 +1953,10 @@ static void enable_link_hdmi(struct pipe_ctx *pipe_ctx)
                stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10;
        if (stream->phy_pix_clk > 340000)
                is_over_340mhz = true;
+       if (dc_is_tmds_signal(stream->signal) && stream->phy_pix_clk > 6000000UL) {
+               ASSERT(false);
+               return;
+       }
 
        if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) {
                unsigned short masked_chip_caps = pipe_ctx->stream->link->chip_caps &