drm/amd/display: Add ASIC cap to limit DCC surface width

[Why]
Certain configurations of DCN401 require ODM4:1 to support DCC for 10K
surfaces. DCC should be conservatively disabled in those cases.

The issue is that current logic limits 10K surface DCC for all
configurations of DCN401.

[How]
Add DC ASIC cap to indicate max surface width that can support DCC.
Disable DCC if this ASIC cap is non-zero and surface width exceeds it.

Reviewed-by: Jun Lei <jun.lei@amd.com>
Signed-off-by: Jerry Zuo <jerry.zuo@amd.com>
Signed-off-by: George Shen <george.shen@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 900892855436e1763ca746ceb4b660e1f00bab9c..55b94a72ddc25dddbaefa8cc5b8802b86fb67136 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -293,6 +293,8 @@ struct dc_caps {
        bool cursor_not_scaled;
        bool dcmode_power_limits_present;
        bool sequential_ono;
+       /* Conservative limit for DCC cases which require ODM4:1 to support*/
+       uint32_t dcc_plane_width_limit;
 };
 
 struct dc_bug_wa {

diff --git a/drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c b/drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
index 5126d603f0b15f07032f57389f8203c54f727c60..181041d6d177c089b507f30c43cb2014b429b0fb 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
+++ b/drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
@@ -829,6 +829,7 @@ bool hubbub401_get_dcc_compression_cap(struct hubbub *hubbub,
                struct dc_surface_dcc_cap *output)
 {
        struct dc *dc = hubbub->ctx->dc;
+       const unsigned int max_dcc_plane_width = dc->caps.dcc_plane_width_limit;
        /* DCN4_Programming_Guide_DCHUB.docx, Section 5.11.2.2 */
        enum dcc_control dcc_control;
        unsigned int plane0_bpe, plane1_bpe;
@@ -843,6 +844,11 @@ bool hubbub401_get_dcc_compression_cap(struct hubbub *hubbub,
        if (dc->debug.disable_dcc == DCC_DISABLE)
                return false;
 
+       /* Conservatively disable DCC for cases where ODM4:1 may be required. */
+       if (max_dcc_plane_width != 0 &&
+                       (input->surface_size.width > max_dcc_plane_width || input->plane1_size.width > max_dcc_plane_width))
+               return false;
+
        switch (input->format) {
        default:
                is_dual_plane = false;

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
index 4e27d2cee9fb5738f7be91705ce6101254f98fdd..a05a2209a44e67dc3fea45a6d8e7e785cb379d0f 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
@@ -1822,6 +1822,9 @@ static bool dcn401_resource_construct(
        dc->caps.extended_aux_timeout_support = true;
        dc->caps.dmcub_support = true;
 
+       if (ASICREV_IS_GC_12_0_1_A0(dc->ctx->asic_id.hw_internal_rev))
+               dc->caps.dcc_plane_width_limit = 7680;
+
        /* Color pipeline capabilities */
        dc->caps.color.dpp.dcn_arch = 1;
        dc->caps.color.dpp.input_lut_shared = 0;