arm64: dts: mediatek: Add socinfo efuses to MT8173/83/96/92/95 SoCs

Add efuse nodes for socinfo retrieval for MT8173, MT8183, MT8186,
MT8192 and MT8195.

Signed-off-by: William-tw Lin <william-tw.lin@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20231222080739.21706-2-william-tw.lin@mediatek.com
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index cac4cd0a032012be0e004eb83baa6515f0f961c0..fe572a2f8f79e38a0452fcc8db844b916e88dfcc 100644 (file)
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -590,6 +590,15 @@
                        reg = <0 0x10206000 0 0x1000>;
                        #address-cells = <1>;
                        #size-cells = <1>;
+
+                       socinfo-data1@40 {
+                               reg = <0x040 0x4>;
+                       };
+
+                       socinfo-data2@44 {
+                               reg = <0x044 0x4>;
+                       };
+
                        thermal_calibration: calib@528 {
                                reg = <0x528 0xc>;
                        };

diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index 920ee415ef5fbd225f4d8e7babe39c609597e0e0..cdc8d86cb432767406e815becaeb6bafaa01f4c2 100644 (file)
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -1585,6 +1585,15 @@
                        reg = <0 0x11f10000 0 0x1000>;
                        #address-cells = <1>;
                        #size-cells = <1>;
+
+                       socinfo-data1@4c {
+                               reg = <0x04c 0x4>;
+                       };
+
+                       socinfo-data2@60 {
+                               reg = <0x060 0x4>;
+                       };
+
                        thermal_calibration: calib@180 {
                                reg = <0x180 0xc>;
                        };

diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
index 2fec6fd1c1a71db7477f4d211ff7be8750761264..c9caa8ab059215c187086b1f994cb2bbba8996b5 100644 (file)
--- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
@@ -1672,6 +1672,10 @@
                                reg = <0x59c 0x4>;
                                bits = <0 3>;
                        };
+
+                       socinfo-data1@7a0 {
+                               reg = <0x7a0 0x4>;
+                       };
                };
 
                mipi_tx0: dsi-phy@11cc0000 {

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 6dd32dbfb832e7d8cdbb7c8a1c8098c6834329de..e2ae1227f3d16c231467aa4f481b77c67f3675e7 100644 (file)
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -1164,6 +1164,14 @@
                        #address-cells = <1>;
                        #size-cells = <1>;
 
+                       socinfo-data1@44 {
+                               reg = <0x044 0x4>;
+                       };
+
+                       socinfo-data2@50 {
+                               reg = <0x050 0x4>;
+                       };
+
                        lvts_e_data1: data1@1c0 {
                                reg = <0x1c0 0x58>;
                        };

diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index b9101662ce40d056295b799120a34c26f04e910d..4f3fcd8c287b483c3824acd3c289221ca86777d8 100644 (file)
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -1701,6 +1701,9 @@
                        svs_calib_data: svs-calib@580 {
                                reg = <0x580 0x64>;
                        };
+                       socinfo-data1@7a0 {
+                               reg = <0x7a0 0x4>;
+                       };
                };
 
                u3phy2: t-phy@11c40000 {