drm/amd/display: Allow Latency Increase For Last Strategy
authorAustin Zheng <Austin.Zheng@amd.com>
Thu, 26 Sep 2024 20:18:10 +0000 (16:18 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Mon, 7 Oct 2024 18:16:31 +0000 (14:16 -0400)
[Why]
Playing 1080p video on 4k60 timing uses UCLK DPM5 and mode support
determines that p-state switching is not supported.

[How]
Allow DML to increase latency as the last strategy so strategies such
as VBlank p-state switching may become possible

Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Signed-off-by: Austin Zheng <Austin.Zheng@amd.com>
Signed-off-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

index 1cf9015e854a961ae11184d2c11224aca1388a21..5a09dd298e6f3c21d43e27eff2308c01a8a86fa9 100644 (file)
@@ -1798,6 +1798,7 @@ bool pmo_dcn4_fams2_init_for_pstate_support(struct dml2_pmo_init_for_pstate_supp
        }
 
        if (s->pmo_dcn4.num_pstate_candidates > 0) {
+               s->pmo_dcn4.pstate_strategy_candidates[s->pmo_dcn4.num_pstate_candidates - 1].allow_state_increase = true;
                s->pmo_dcn4.cur_pstate_candidate = -1;
                return true;
        } else {