xhci: Add USB4 tunnel detection for USB3 devices on Intel hosts

Knowledge about tunneled devices is useful in order to correctly describe
the relationship between tunneled USB3 device and USB4 Host Interface,
ensuring proper suspend and resume order, and to be able to power down
Thunderbolt if there is no need for tunneling.

Intel hosts share if a USB3 connection is native or tunneled via vendor
specific "SPR eSS PORT" registers.

These vendor registers are available if host supports a vendor specific
SPR shadow extended capability with ID 206. Registers are per USB3 port
and 0x20 apart.

Knowing the tunneling status of the device connected to roothub is enough
as all its children will have the same status.

Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>
Link: https://lore.kernel.org/r/20240830152630.3943215-2-mathias.nyman@linux.intel.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/usb/host/xhci-ext-caps.h b/drivers/usb/host/xhci-ext-caps.h
index 96eb36a587382609c45a9023700d8f8d9101616a..67ecf7320c6239c1a61882db5b9640d60587ccf3 100644 (file)
--- a/drivers/usb/host/xhci-ext-caps.h
+++ b/drivers/usb/host/xhci-ext-caps.h
@@ -42,6 +42,7 @@
 #define XHCI_EXT_CAPS_DEBUG    10
 /* Vendor caps */
 #define XHCI_EXT_CAPS_VENDOR_INTEL     192
+#define XHCI_EXT_CAPS_INTEL_SPR_SHADOW 206
 /* USB Legacy Support Capability - section 7.1.1 */
 #define XHCI_HC_BIOS_OWNED     (1 << 16)
 #define XHCI_HC_OS_OWNED       (1 << 24)
@@ -64,6 +65,10 @@
 #define XHCI_HLC               (1 << 19)
 #define XHCI_BLC               (1 << 20)
 
+/* Intel SPR shadow capability */
+#define XHCI_INTEL_SPR_ESS_PORT_OFFSET  0x8ac4 /* SuperSpeed port control */
+#define XHCI_INTEL_SPR_TUNEN   BIT(4)          /* Tunnel mode enabled */
+
 /* command register values to disable interrupts and halt the HC */
 /* start/stop HC execution - do not write unless HC is halted*/
 #define XHCI_CMD_RUN           (1 << 0)

diff --git a/drivers/usb/host/xhci-hub.c b/drivers/usb/host/xhci-hub.c
index 61f083de6e196744ea3e6655a86c83581ce34d10..4ba910eadd3fdf10cbc20fbcba924863c07d759d 100644 (file)
--- a/drivers/usb/host/xhci-hub.c
+++ b/drivers/usb/host/xhci-hub.c
@@ -752,6 +752,37 @@ static int xhci_exit_test_mode(struct xhci_hcd *xhci)
        return xhci_reset(xhci, XHCI_RESET_SHORT_USEC);
 }
 
+/**
+ * xhci_port_is_tunneled() - Check if USB3 connection is tunneled over USB4
+ * @xhci: xhci host controller
+ * @port: USB3 port to be checked.
+ *
+ * Some hosts can detect if a USB3 connection is native USB3 or tunneled over
+ * USB4. Intel hosts expose this via vendor specific extended capability 206
+ * eSS PORT registers TUNEN (tunnel enabled) bit.
+ *
+ * A USB3 device must be connected to the port to detect the tunnel.
+ *
+ * Return: true if USB3 connection is tunneled over USB4
+ */
+bool xhci_port_is_tunneled(struct xhci_hcd *xhci, struct xhci_port *port)
+{
+       void __iomem *base;
+       u32 offset;
+
+       base = &xhci->cap_regs->hc_capbase;
+       offset = xhci_find_next_ext_cap(base, 0, XHCI_EXT_CAPS_INTEL_SPR_SHADOW);
+
+       if (offset && offset <= XHCI_INTEL_SPR_ESS_PORT_OFFSET) {
+               offset = XHCI_INTEL_SPR_ESS_PORT_OFFSET + port->hcd_portnum * 0x20;
+
+               if (readl(base + offset) & XHCI_INTEL_SPR_TUNEN)
+                       return true;
+       }
+
+       return false;
+}
+
 void xhci_set_link_state(struct xhci_hcd *xhci, struct xhci_port *port,
                         u32 link_state)
 {

diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
index efdf4c228b8c0ace31ac8d956fbb1466971fe976..1ea2c91106b7b26ca52fc403f0c8410bca118256 100644 (file)
--- a/drivers/usb/host/xhci.c
+++ b/drivers/usb/host/xhci.c
@@ -4525,6 +4525,17 @@ static int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
        struct xhci_port *port;
        u32 capability;
 
+       /* Check if USB3 device at root port is tunneled over USB4 */
+       if (hcd->speed >= HCD_USB3 && !udev->parent->parent) {
+               port = xhci->usb3_rhub.ports[udev->portnum - 1];
+
+               if (xhci_port_is_tunneled(xhci, port))
+                       dev_dbg(&udev->dev, "tunneled over USB4 link\n");
+               else
+                       dev_dbg(&udev->dev, "native USB 3.x link\n");
+               return 0;
+       }
+
        if (hcd->speed >= HCD_USB3 || !udev->lpm_capable || !xhci->hw_lpm_support)
                return 0;
 

diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h
index df2c81db21a13445b1268fe5445bcae51b850b8f..e87a6b2f139d1d271fd08888947c0c4195f18184 100644 (file)
--- a/drivers/usb/host/xhci.h
+++ b/drivers/usb/host/xhci.h
@@ -1929,6 +1929,7 @@ int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex,
 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf);
 int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1);
 struct xhci_hub *xhci_get_rhub(struct usb_hcd *hcd);
+bool xhci_port_is_tunneled(struct xhci_hcd *xhci, struct xhci_port *port);
 
 void xhci_hc_died(struct xhci_hcd *xhci);