drm/msm: Fix section names and sizes

The section names randomly appended _DATA or _ADDR in many cases, and/or
didn't match the reg names.  Fix them so crashdec can properly resolve
the section names back to reg names.

Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/666654/

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h
index 95d93ac6812a4da05afe02d8072db31b6a5ae46c..1c18499b60bb9b328ac917369c803e3574ba094b 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h
@@ -419,47 +419,47 @@ static const struct a6xx_indexed_registers a6xx_indexed_reglist[] = {
                REG_A6XX_CP_SQE_STAT_DATA, 0x33, NULL },
        { "CP_DRAW_STATE", REG_A6XX_CP_DRAW_STATE_ADDR,
                REG_A6XX_CP_DRAW_STATE_DATA, 0x100, NULL },
-       { "CP_UCODE_DBG_DATA", REG_A6XX_CP_SQE_UCODE_DBG_ADDR,
+       { "CP_SQE_UCODE_DBG", REG_A6XX_CP_SQE_UCODE_DBG_ADDR,
                REG_A6XX_CP_SQE_UCODE_DBG_DATA, 0x8000, NULL },
-       { "CP_ROQ", REG_A6XX_CP_ROQ_DBG_ADDR,
+       { "CP_ROQ_DBG", REG_A6XX_CP_ROQ_DBG_ADDR,
                REG_A6XX_CP_ROQ_DBG_DATA, 0, a6xx_get_cp_roq_size},
 };
 
 static const struct a6xx_indexed_registers a7xx_indexed_reglist[] = {
        { "CP_SQE_STAT", REG_A6XX_CP_SQE_STAT_ADDR,
-               REG_A6XX_CP_SQE_STAT_DATA, 0x33, NULL },
+               REG_A6XX_CP_SQE_STAT_DATA, 0x40, NULL },
        { "CP_DRAW_STATE", REG_A6XX_CP_DRAW_STATE_ADDR,
                REG_A6XX_CP_DRAW_STATE_DATA, 0x100, NULL },
-       { "CP_UCODE_DBG_DATA", REG_A6XX_CP_SQE_UCODE_DBG_ADDR,
+       { "CP_SQE_UCODE_DBG", REG_A6XX_CP_SQE_UCODE_DBG_ADDR,
                REG_A6XX_CP_SQE_UCODE_DBG_DATA, 0x8000, NULL },
-       { "CP_BV_SQE_STAT_ADDR", REG_A7XX_CP_BV_SQE_STAT_ADDR,
-               REG_A7XX_CP_BV_SQE_STAT_DATA, 0x33, NULL },
-       { "CP_BV_DRAW_STATE_ADDR", REG_A7XX_CP_BV_DRAW_STATE_ADDR,
+       { "CP_BV_SQE_STAT", REG_A7XX_CP_BV_SQE_STAT_ADDR,
+               REG_A7XX_CP_BV_SQE_STAT_DATA, 0x40, NULL },
+       { "CP_BV_DRAW_STATE", REG_A7XX_CP_BV_DRAW_STATE_ADDR,
                REG_A7XX_CP_BV_DRAW_STATE_DATA, 0x100, NULL },
-       { "CP_BV_SQE_UCODE_DBG_ADDR", REG_A7XX_CP_BV_SQE_UCODE_DBG_ADDR,
+       { "CP_BV_SQE_UCODE_DBG", REG_A7XX_CP_BV_SQE_UCODE_DBG_ADDR,
                REG_A7XX_CP_BV_SQE_UCODE_DBG_DATA, 0x8000, NULL },
-       { "CP_SQE_AC_STAT_ADDR", REG_A7XX_CP_SQE_AC_STAT_ADDR,
-               REG_A7XX_CP_SQE_AC_STAT_DATA, 0x33, NULL },
-       { "CP_LPAC_DRAW_STATE_ADDR", REG_A7XX_CP_LPAC_DRAW_STATE_ADDR,
+       { "CP_SQE_AC_STAT", REG_A7XX_CP_SQE_AC_STAT_ADDR,
+               REG_A7XX_CP_SQE_AC_STAT_DATA, 0x40, NULL },
+       { "CP_LPAC_DRAW_STATE", REG_A7XX_CP_LPAC_DRAW_STATE_ADDR,
                REG_A7XX_CP_LPAC_DRAW_STATE_DATA, 0x100, NULL },
-       { "CP_SQE_AC_UCODE_DBG_ADDR", REG_A7XX_CP_SQE_AC_UCODE_DBG_ADDR,
+       { "CP_SQE_AC_UCODE_DBG", REG_A7XX_CP_SQE_AC_UCODE_DBG_ADDR,
                REG_A7XX_CP_SQE_AC_UCODE_DBG_DATA, 0x8000, NULL },
-       { "CP_LPAC_FIFO_DBG_ADDR", REG_A7XX_CP_LPAC_FIFO_DBG_ADDR,
+       { "CP_LPAC_FIFO_DBG", REG_A7XX_CP_LPAC_FIFO_DBG_ADDR,
                REG_A7XX_CP_LPAC_FIFO_DBG_DATA, 0x40, NULL },
-       { "CP_ROQ", REG_A6XX_CP_ROQ_DBG_ADDR,
+       { "CP_ROQ_DBG", REG_A6XX_CP_ROQ_DBG_ADDR,
                REG_A6XX_CP_ROQ_DBG_DATA, 0, a7xx_get_cp_roq_size },
 };
 
 static const struct a6xx_indexed_registers a6xx_cp_mempool_indexed = {
-       "CP_MEMPOOL", REG_A6XX_CP_MEM_POOL_DBG_ADDR,
+       "CP_MEM_POOL_DBG", REG_A6XX_CP_MEM_POOL_DBG_ADDR,
                REG_A6XX_CP_MEM_POOL_DBG_DATA, 0x2060, NULL,
 };
 
 static const struct a6xx_indexed_registers a7xx_cp_bv_mempool_indexed[] = {
-       { "CP_MEMPOOL", REG_A6XX_CP_MEM_POOL_DBG_ADDR,
-               REG_A6XX_CP_MEM_POOL_DBG_DATA, 0x2100, NULL },
-       { "CP_BV_MEMPOOL", REG_A7XX_CP_BV_MEM_POOL_DBG_ADDR,
-               REG_A7XX_CP_BV_MEM_POOL_DBG_DATA, 0x2100, NULL },
+       { "CP_MEM_POOL_DBG", REG_A6XX_CP_MEM_POOL_DBG_ADDR,
+               REG_A6XX_CP_MEM_POOL_DBG_DATA, 0x2200, NULL },
+       { "CP_BV_MEM_POOL_DBG", REG_A7XX_CP_BV_MEM_POOL_DBG_ADDR,
+               REG_A7XX_CP_BV_MEM_POOL_DBG_DATA, 0x2200, NULL },
 };
 
 #define DEBUGBUS(_id, _count) { .id = _id, .name = #_id, .count = _count }

diff --git a/drivers/gpu/drm/msm/adreno/adreno_gen7_9_0_snapshot.h b/drivers/gpu/drm/msm/adreno/adreno_gen7_9_0_snapshot.h
index e02cabb39f194c7be12e26711a326544ef448f47..b1f8bbf1d843bc49d9501f443176ac15fef36858 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/adreno_gen7_9_0_snapshot.h
+++ b/drivers/gpu/drm/msm/adreno/adreno_gen7_9_0_snapshot.h
@@ -1299,29 +1299,29 @@ static struct a6xx_indexed_registers gen7_9_0_cp_indexed_reg_list[] = {
                REG_A6XX_CP_SQE_STAT_DATA, 0x00040},
        { "CP_DRAW_STATE", REG_A6XX_CP_DRAW_STATE_ADDR,
                REG_A6XX_CP_DRAW_STATE_DATA, 0x00200},
-       { "CP_ROQ", REG_A6XX_CP_ROQ_DBG_ADDR,
+       { "CP_ROQ_DBG", REG_A6XX_CP_ROQ_DBG_ADDR,
                REG_A6XX_CP_ROQ_DBG_DATA, 0x00800},
-       { "CP_UCODE_DBG_DATA", REG_A6XX_CP_SQE_UCODE_DBG_ADDR,
+       { "CP_SQE_UCODE_DBG", REG_A6XX_CP_SQE_UCODE_DBG_ADDR,
                REG_A6XX_CP_SQE_UCODE_DBG_DATA, 0x08000},
-       { "CP_BV_DRAW_STATE_ADDR", REG_A7XX_CP_BV_DRAW_STATE_ADDR,
+       { "CP_BV_DRAW_STATE", REG_A7XX_CP_BV_DRAW_STATE_ADDR,
                REG_A7XX_CP_BV_DRAW_STATE_DATA, 0x00200},
-       { "CP_BV_ROQ_DBG_ADDR", REG_A7XX_CP_BV_ROQ_DBG_ADDR,
+       { "CP_BV_ROQ_DBG", REG_A7XX_CP_BV_ROQ_DBG_ADDR,
                REG_A7XX_CP_BV_ROQ_DBG_DATA, 0x00800},
-       { "CP_BV_SQE_UCODE_DBG_ADDR", REG_A7XX_CP_BV_SQE_UCODE_DBG_ADDR,
+       { "CP_BV_SQE_UCODE_DBG", REG_A7XX_CP_BV_SQE_UCODE_DBG_ADDR,
                REG_A7XX_CP_BV_SQE_UCODE_DBG_DATA, 0x08000},
-       { "CP_BV_SQE_STAT_ADDR", REG_A7XX_CP_BV_SQE_STAT_ADDR,
+       { "CP_BV_SQE_STAT", REG_A7XX_CP_BV_SQE_STAT_ADDR,
                REG_A7XX_CP_BV_SQE_STAT_DATA, 0x00040},
-       { "CP_RESOURCE_TBL", REG_A7XX_CP_RESOURCE_TABLE_DBG_ADDR,
+       { "CP_RESOURCE_TABLE_DBG", REG_A7XX_CP_RESOURCE_TABLE_DBG_ADDR,
                REG_A7XX_CP_RESOURCE_TABLE_DBG_DATA, 0x04100},
-       { "CP_LPAC_DRAW_STATE_ADDR", REG_A7XX_CP_LPAC_DRAW_STATE_ADDR,
+       { "CP_LPAC_DRAW_STATE", REG_A7XX_CP_LPAC_DRAW_STATE_ADDR,
                REG_A7XX_CP_LPAC_DRAW_STATE_DATA, 0x00200},
-       { "CP_LPAC_ROQ", REG_A7XX_CP_LPAC_ROQ_DBG_ADDR,
+       { "CP_LPAC_ROQ_DBG", REG_A7XX_CP_LPAC_ROQ_DBG_ADDR,
                REG_A7XX_CP_LPAC_ROQ_DBG_DATA, 0x00200},
-       { "CP_SQE_AC_UCODE_DBG_ADDR", REG_A7XX_CP_SQE_AC_UCODE_DBG_ADDR,
+       { "CP_SQE_AC_UCODE_DBG", REG_A7XX_CP_SQE_AC_UCODE_DBG_ADDR,
                REG_A7XX_CP_SQE_AC_UCODE_DBG_DATA, 0x08000},
-       { "CP_SQE_AC_STAT_ADDR", REG_A7XX_CP_SQE_AC_STAT_ADDR,
+       { "CP_SQE_AC_STAT", REG_A7XX_CP_SQE_AC_STAT_ADDR,
                REG_A7XX_CP_SQE_AC_STAT_DATA, 0x00040},
-       { "CP_LPAC_FIFO_DBG_ADDR", REG_A7XX_CP_LPAC_FIFO_DBG_ADDR,
+       { "CP_LPAC_FIFO_DBG", REG_A7XX_CP_LPAC_FIFO_DBG_ADDR,
                REG_A7XX_CP_LPAC_FIFO_DBG_DATA, 0x00040},
        { "CP_AQE_ROQ_0", REG_A7XX_CP_AQE_ROQ_DBG_ADDR_0,
                REG_A7XX_CP_AQE_ROQ_DBG_DATA_0, 0x00100},