arm64: dts: imx8mp-phyboard-pollux-rdk: Add support for PCIe

Add support for the Mini PCIe slot.

Signed-off-by: Benjamin Hahn <B.Hahn@phytec.de>
Reviewed-by: Yannic Moog <y.moog@phytec.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts
index f7ac9a0b5ff050b4fd2ca3f52ea4ff9aef808cf0..50debe821c4212464bf87a5fbfa96b2403f1a186 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts
@@ -6,6 +6,7 @@
 
 /dts-v1/;
 
+#include <dt-bindings/phy/phy-imx8-pcie.h>
 #include <dt-bindings/leds/leds-pca9532.h>
 #include <dt-bindings/pwm/pwm.h>
 #include "imx8mp-phycore-som.dtsi"
@@ -221,6 +222,23 @@
        status = "okay";
 };
 
+&pcie_phy {
+       clocks = <&hsio_blk_ctrl>;
+       clock-names = "ref";
+       fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>;
+       fsl,clkreq-unsupported;
+       status = "okay";
+};
+
+/* Mini PCIe */
+&pcie {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_pcie0>;
+       reset-gpio = <&gpio1 8 GPIO_ACTIVE_LOW>;
+       vpcie-supply = <&reg_vcc_3v3_sw>;
+       status = "okay";
+};
+
 &pwm3 {
        status = "okay";
        pinctrl-names = "default";
@@ -405,6 +423,15 @@
                >;
        };
 
+       pinctrl_pcie0: pcie0grp {
+               fsl,pins = <
+                       MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08     0x40
+                       MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10     0x60
+                       MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11     0x60 /* open drain, pull up */
+                       MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14     0x40
+               >;
+       };
+
        pinctrl_pwm3: pwm3grp {
                fsl,pins = <
                        MX8MP_IOMUXC_SPDIF_TX__PWM3_OUT         0x12