drm/i915: Assert that the request->tail is always qword aligned

The hardware requires that the tail pointer only advance in qword units,
so assert that the value we write is aligned to qwords, and similarly
enforce this restriction onto the request->tail.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20170217163833.731-1-chris@chris-wilson.co.uk
Reviewed-by: Michał Winiarski <michal.winiarski@intel.com>

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index afcb1f18916216efa886621e15ed633667badcb6..d6b67be4715d98803f28c14f8cf404110f0474e4 100644 (file)
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -325,6 +325,7 @@ static u64 execlists_update_context(struct drm_i915_gem_request *rq)
                rq->ctx->ppgtt ?: rq->i915->mm.aliasing_ppgtt;
        u32 *reg_state = ce->lrc_reg_state;
 
+       GEM_BUG_ON(!IS_ALIGNED(rq->tail, 8));
        reg_state[CTX_RING_TAIL+1] = rq->tail;
 
        /* True 32b PPGTT with dynamic page allocation: update PDP
@@ -1283,6 +1284,7 @@ static void reset_common_ring(struct intel_engine_cs *engine,
 
        /* Reset WaIdleLiteRestore:bdw,skl as well */
        request->tail = request->wa_tail - WA_TAIL_DWORDS * sizeof(u32);
+       GEM_BUG_ON(!IS_ALIGNED(request->tail, 8));
 }
 
 static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request *req)
@@ -1494,6 +1496,7 @@ static void gen8_emit_breadcrumb(struct drm_i915_gem_request *request, u32 *cs)
        *cs++ = MI_USER_INTERRUPT;
        *cs++ = MI_NOOP;
        request->tail = intel_ring_offset(request, cs);
+       GEM_BUG_ON(!IS_ALIGNED(request->tail, 8));
 
        gen8_emit_wa_tail(request, cs);
 }
@@ -1521,6 +1524,7 @@ static void gen8_emit_breadcrumb_render(struct drm_i915_gem_request *request,
        *cs++ = MI_USER_INTERRUPT;
        *cs++ = MI_NOOP;
        request->tail = intel_ring_offset(request, cs);
+       GEM_BUG_ON(!IS_ALIGNED(request->tail, 8));
 
        gen8_emit_wa_tail(request, cs);
 }

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index d56f384938f7e626bc0d2b5496e0a2be890b2990..f62afffef68203feced8fe52810af2b2c1613e9e 100644 (file)
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -784,6 +784,7 @@ static void i9xx_submit_request(struct drm_i915_gem_request *request)
 
        i915_gem_request_submit(request);
 
+       GEM_BUG_ON(!IS_ALIGNED(request->tail, 8));
        I915_WRITE_TAIL(request->engine, request->tail);
 }
 
@@ -795,6 +796,7 @@ static void i9xx_emit_breadcrumb(struct drm_i915_gem_request *req, u32 *cs)
        *cs++ = MI_USER_INTERRUPT;
 
        req->tail = intel_ring_offset(req, cs);
+       GEM_BUG_ON(!IS_ALIGNED(req->tail, 8));
 }
 
 static const int i9xx_emit_breadcrumb_sz = 4;
@@ -833,6 +835,7 @@ static void gen8_render_emit_breadcrumb(struct drm_i915_gem_request *req,
        *cs++ = MI_NOOP;
 
        req->tail = intel_ring_offset(req, cs);
+       GEM_BUG_ON(!IS_ALIGNED(req->tail, 8));
 }
 
 static const int gen8_render_emit_breadcrumb_sz = 8;