clk: renesas: r9a09g057: Add clock and reset entries for USB2

Add clock and reset entries for USB2.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250407165202.197570-9-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/r9a09g057-cpg.c b/drivers/clk/renesas/r9a09g057-cpg.c
index da20dbaead1f6e7b0d95aeb06bd948dc2e9836cf..3c40e36259fe3fc550dcbb2a88bb7b660caa9239 100644 (file)
--- a/drivers/clk/renesas/r9a09g057-cpg.c
+++ b/drivers/clk/renesas/r9a09g057-cpg.c
@@ -16,7 +16,7 @@
 
 enum clk_ids {
        /* Core Clock Outputs exported to DT */
-       LAST_DT_CORE_CLK = R9A09G057_IOTOP_0_SHCLK,
+       LAST_DT_CORE_CLK = R9A09G057_GBETH_1_CLK_PTP_REF_I,
 
        /* External Input Clocks */
        CLK_AUDIO_EXTAL,
@@ -41,6 +41,7 @@ enum clk_ids {
        CLK_PLLDTY_ACPU,
        CLK_PLLDTY_ACPU_DIV2,
        CLK_PLLDTY_ACPU_DIV4,
+       CLK_PLLDTY_DIV8,
        CLK_PLLDTY_DIV16,
        CLK_PLLDTY_RCPU,
        CLK_PLLDTY_RCPU_DIV4,
@@ -104,6 +105,7 @@ static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = {
        DEF_DDIV(".plldty_acpu", CLK_PLLDTY_ACPU, CLK_PLLDTY, CDDIV0_DIVCTL2, dtable_2_64),
        DEF_FIXED(".plldty_acpu_div2", CLK_PLLDTY_ACPU_DIV2, CLK_PLLDTY_ACPU, 1, 2),
        DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1, 4),
+       DEF_FIXED(".plldty_div8", CLK_PLLDTY_DIV8, CLK_PLLDTY, 1, 8),
        DEF_FIXED(".plldty_div16", CLK_PLLDTY_DIV16, CLK_PLLDTY, 1, 16),
        DEF_DDIV(".plldty_rcpu", CLK_PLLDTY_RCPU, CLK_PLLDTY, CDDIV3_DIVCTL2, dtable_2_64),
        DEF_FIXED(".plldty_rcpu_div4", CLK_PLLDTY_RCPU_DIV4, CLK_PLLDTY_RCPU, 1, 4),
@@ -126,6 +128,8 @@ static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = {
        DEF_DDIV("ca55_0_coreclk3", R9A09G057_CA55_0_CORE_CLK3, CLK_PLLCA55,
                 CDDIV1_DIVCTL3, dtable_1_8),
        DEF_FIXED("iotop_0_shclk", R9A09G057_IOTOP_0_SHCLK, CLK_PLLCM33_DIV16, 1, 1),
+       DEF_FIXED("usb2_0_clk_core0", R9A09G057_USB2_0_CLK_CORE0, CLK_QEXTAL, 1, 1),
+       DEF_FIXED("usb2_0_clk_core1", R9A09G057_USB2_0_CLK_CORE1, CLK_QEXTAL, 1, 1),
 };
 
 static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = {
@@ -219,6 +223,16 @@ static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = {
                                                BUS_MSTOP(8, BIT(4))),
        DEF_MOD("sdhi_2_aclk",                  CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14,
                                                BUS_MSTOP(8, BIT(4))),
+       DEF_MOD("usb2_0_u2h0_hclk",             CLK_PLLDTY_DIV8, 11, 3, 5, 19,
+                                               BUS_MSTOP(7, BIT(7))),
+       DEF_MOD("usb2_0_u2h1_hclk",             CLK_PLLDTY_DIV8, 11, 4, 5, 20,
+                                               BUS_MSTOP(7, BIT(8))),
+       DEF_MOD("usb2_0_u2p_exr_cpuclk",        CLK_PLLDTY_ACPU_DIV4, 11, 5, 5, 21,
+                                               BUS_MSTOP(7, BIT(9))),
+       DEF_MOD("usb2_0_pclk_usbtst0",          CLK_PLLDTY_ACPU_DIV4, 11, 6, 5, 22,
+                                               BUS_MSTOP(7, BIT(10))),
+       DEF_MOD("usb2_0_pclk_usbtst1",          CLK_PLLDTY_ACPU_DIV4, 11, 7, 5, 23,
+                                               BUS_MSTOP(7, BIT(11))),
        DEF_MOD("cru_0_aclk",                   CLK_PLLDTY_ACPU_DIV2, 13, 2, 6, 18,
                                                BUS_MSTOP(9, BIT(4))),
        DEF_MOD_NO_PM("cru_0_vclk",             CLK_PLLVDO_CRU0, 13, 3, 6, 19,
@@ -286,6 +300,10 @@ static const struct rzv2h_reset r9a09g057_resets[] __initconst = {
        DEF_RST(10, 7, 4, 24),          /* SDHI_0_IXRST */
        DEF_RST(10, 8, 4, 25),          /* SDHI_1_IXRST */
        DEF_RST(10, 9, 4, 26),          /* SDHI_2_IXRST */
+       DEF_RST(10, 12, 4, 29),         /* USB2_0_U2H0_HRESETN */
+       DEF_RST(10, 13, 4, 30),         /* USB2_0_U2H1_HRESETN */
+       DEF_RST(10, 14, 4, 31),         /* USB2_0_U2P_EXL_SYSRST */
+       DEF_RST(10, 15, 5, 0),          /* USB2_0_PRESETN */
        DEF_RST(12, 5, 5, 22),          /* CRU_0_PRESETN */
        DEF_RST(12, 6, 5, 23),          /* CRU_0_ARESETN */
        DEF_RST(12, 7, 5, 24),          /* CRU_0_S_RESETN */