clk: renesas: r9a09g047: Add clock and reset entries for GE3D

Add CLK_PLLVDO_GPU along with the necessary clock and reset entries for
GE3D.

Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250402131142.1270701-2-tommaso.merciai.xr@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/r9a09g047-cpg.c b/drivers/clk/renesas/r9a09g047-cpg.c
index 7b9311af603eccdea7e053d15312afbc68f32480..88a5a1c24adee2620e36c17f3fada2f7e28f3130 100644 (file)
--- a/drivers/clk/renesas/r9a09g047-cpg.c
+++ b/drivers/clk/renesas/r9a09g047-cpg.c
@@ -41,6 +41,7 @@ enum clk_ids {
        CLK_PLLDTY_ACPU_DIV4,
        CLK_PLLDTY_DIV16,
        CLK_PLLVDO_CRU0,
+       CLK_PLLVDO_GPU,
 
        /* Module Clocks */
        MOD_CLK_BASE,
@@ -96,6 +97,7 @@ static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = {
        DEF_FIXED(".plldty_div16", CLK_PLLDTY_DIV16, CLK_PLLDTY, 1, 16),
 
        DEF_DDIV(".pllvdo_cru0", CLK_PLLVDO_CRU0, CLK_PLLVDO, CDDIV3_DIVCTL3, dtable_2_4),
+       DEF_DDIV(".pllvdo_gpu", CLK_PLLVDO_GPU, CLK_PLLVDO, CDDIV3_DIVCTL1, dtable_2_64),
 
        /* Core Clocks */
        DEF_FIXED("sys_0_pclk", R9A09G047_SYS_0_PCLK, CLK_QEXTAL, 1, 1),
@@ -183,6 +185,12 @@ static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = {
                                                BUS_MSTOP(9, BIT(4))),
        DEF_MOD("cru_0_pclk",                   CLK_PLLDTY_DIV16, 13, 4, 6, 20,
                                                BUS_MSTOP(9, BIT(4))),
+       DEF_MOD("ge3d_clk",                     CLK_PLLVDO_GPU, 15, 0, 7, 16,
+                                               BUS_MSTOP(3, BIT(4))),
+       DEF_MOD("ge3d_axi_clk",                 CLK_PLLDTY_ACPU_DIV2, 15, 1, 7, 17,
+                                               BUS_MSTOP(3, BIT(4))),
+       DEF_MOD("ge3d_ace_clk",                 CLK_PLLDTY_ACPU_DIV2, 15, 2, 7, 18,
+                                               BUS_MSTOP(3, BIT(4))),
        DEF_MOD("tsu_1_pclk",                   CLK_QEXTAL, 16, 10, 8, 10,
                                                BUS_MSTOP(2, BIT(15))),
 };
@@ -213,6 +221,9 @@ static const struct rzv2h_reset r9a09g047_resets[] __initconst = {
        DEF_RST(12, 5, 5, 22),          /* CRU_0_PRESETN */
        DEF_RST(12, 6, 5, 23),          /* CRU_0_ARESETN */
        DEF_RST(12, 7, 5, 24),          /* CRU_0_S_RESETN */
+       DEF_RST(13, 13, 6, 14),         /* GE3D_RESETN */
+       DEF_RST(13, 14, 6, 15),         /* GE3D_AXI_RESETN */
+       DEF_RST(13, 15, 6, 16),         /* GE3D_ACE_RESETN */
        DEF_RST(15, 8, 7, 9),           /* TSU_1_PRESETN */
 };