drm/radeon: add indirect accessors for UVD CTX registers

These are needed for certain UVD power saving features.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/radeon/r600_reg.h b/drivers/gpu/drm/radeon/r600_reg.h
index 58c86cc051b1a0a3bf312fca241bb5f0c16ec209..3ef202629e7ee37f8aeabc6de7963e121b96a614 100644 (file)
--- a/drivers/gpu/drm/radeon/r600_reg.h
+++ b/drivers/gpu/drm/radeon/r600_reg.h
@@ -34,6 +34,9 @@
 #define R600_RCU_INDEX                      0x0100
 #define R600_RCU_DATA                       0x0104
 
+#define R600_UVD_CTX_INDEX                  0xf4a0
+#define R600_UVD_CTX_DATA                   0xf4a4
+
 #define R600_MC_VM_FB_LOCATION                 0x2180
 #define                R600_MC_FB_BASE_MASK                    0x0000FFFF
 #define                R600_MC_FB_BASE_SHIFT                   0

diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 706b018e019ed587eb97bf7a1e2540de5f1c088d..4ea447d52b62634201aa9919b4c699b4201d62e0 100644 (file)
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -2094,6 +2094,8 @@ void cik_mm_wdoorbell(struct radeon_device *rdev, u32 offset, u32 v);
 #define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v))
 #define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg))
 #define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v))
+#define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg))
+#define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v))
 #define WREG32_P(reg, val, mask)                               \
        do {                                                    \
                uint32_t tmp_ = RREG32(reg);                    \
@@ -2210,6 +2212,21 @@ static inline void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v)
        WREG32(EVERGREEN_PIF_PHY1_DATA, (v));
 }
 
+static inline u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg)
+{
+       u32 r;
+
+       WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
+       r = RREG32(R600_UVD_CTX_DATA);
+       return r;
+}
+
+static inline void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v)
+{
+       WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
+       WREG32(R600_UVD_CTX_DATA, (v));
+}
+
 void r100_pll_errata_after_index(struct radeon_device *rdev);