return ((phase >> 2) & PS_PHASE_MASK) | trip;
}
-#define SKL_MIN_DST_W 8
#define SKL_MAX_DST_W 4096
-#define SKL_MIN_DST_H 8
#define SKL_MAX_DST_H 4096
#define ICL_MAX_DST_W 5120
#define ICL_MAX_DST_H 4096
}
}
+static void skl_scaler_min_dst_size(int *min_w, int *min_h)
+{
+ *min_w = 8;
+ *min_h = 8;
+}
+
static int
skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
unsigned int scaler_user, int *scaler_id,
skl_scaler_min_src_size(format, modifier, &min_src_w, &min_src_h);
skl_scaler_max_src_size(crtc, &max_src_w, &max_src_h);
- min_dst_w = SKL_MIN_DST_W;
- min_dst_h = SKL_MIN_DST_H;
+ skl_scaler_min_dst_size(&min_dst_w, &min_dst_h);
if (DISPLAY_VER(display) < 11) {
max_dst_w = SKL_MAX_DST_W;